TLB Compression for Contiguous Mappings Using Shared Address Bits
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Solution Overview
Problem
Existing memory management techniques in translation lookaside buffers (TLBs) are inefficient in terms of storage and access performance, particularly in resource-constrained environments like mobile devices and machine learning applications, due to the limited capacity and high resource utilization of storing virtual-to-physical address mappings.
Innovation Solution
The proposed method compresses multiple contiguous virtual and physical memory addresses into a single TLB entry by utilizing shared bits and attributes, reducing storage requirements and increasing the number of mappings without increasing the TLB size, through techniques that differentiate between VA and PA contiguity and bit sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple virtual-to-physical address mappings are stored in the TLB, then the number of mappings increases, but the TLB size increases
Solution Approach 1:
The patent merges multiple contiguous physical memory addresses that share common address bits into a single compressed TLB entry. Instead of storing each mapping separately, the common bits are stored once and shared across multiple mappings, effectively combining multiple entries into one compact structure that increases mapping capacity without proportionally increasing TLB size.
Solution Approach 2:
The patent implements a nested structure where compressed TLB entries contain base address information that is further nested with offset information. The base address portion contains common bits shared by multiple physical addresses, while offset portions contain the varying bits, creating a hierarchical nesting that efficiently packs multiple mappings into limited space.
2Measurement precision
If the TLB stores complete physical memory addresses for each mapping, then address translation accuracy is maintained, but storage efficiency decreases
Solution Approach 1:
The patent extracts and separates the common address bits from the varying address bits in contiguous physical memory addresses. The common bits are extracted once and stored in the base address portion, while only the varying offset bits are stored separately. This extraction eliminates redundant storage of identical bits while preserving the complete address information needed for accurate translation.
Solution Approach 2:
The patent applies different storage strategies to different portions of the address based on their characteristics. Base address portions with high similarity across multiple mappings are stored once with high compression, while offset portions with varying values are stored individually. This local quality approach optimizes storage efficiency for each segment according to its specific properties while maintaining overall translation accuracy.
Data Source
AI summary
Certain aspects of the present disclosure provide techniques and apparatus for translation lookaside buffer (TLB) compression. Embodiments include determining that a plurality of physical memory addresses, associated with a plurality of virtual memory addresses, are contiguous with one another and share one or more common address bits or one or more common attribute bits, wherein each respective physical memory address of the plurality of physical memory addresses corresponds to a separate respective physical memory page. Embodiments include generating a tag for an entry in a TLB, the tag representing the plurality of virtual memory addresses. Embodiments include associating, in the entry in the TLB, the tag with data comprising: a single instance of the one or more common address bits or the one or more common attribute bits of the plurality of physical memory addresses; and other bits of the plurality of physical memory addresses.