Shared Row and Column Address Bus Reduces Memory Layout Congestion
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Solution Overview
Problem
The existing memory device architecture has a high number of signal lines between the central logic region and the bank logic regions, leading to congestion and limited flexibility in layout design.
Innovation Solution
Implementing a shared row and column address bus system, where central row and column address latches are coupled to associated bank latches via a shared address bus, reducing the number of signal lines and allowing for more flexible layout arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate row and column address buses are used to connect central logic region to bank logic regions, then address signals can be transmitted reliably, but the number of signal lines increases leading to congestion and reduced layout flexibility
Solution Approach 1:
The patent merges separate row address bus and column address bus into a single shared address bus. The shared bus carries both row and column address signals alternately, reducing the total number of signal lines between central logic region and bank logic regions while maintaining reliable address transmission through time-division multiplexing.
Solution Approach 2:
The patent introduces dynamic control mechanisms including a multiplexer at the central logic region and corresponding demultiplexers at bank logic regions. These dynamic switching elements route row or column addresses onto the shared bus based on timing signals, enabling flexible signal allocation over time while reducing spatial complexity.
2Productivity
If more signal lines are provided between central region and bank logic regions, then more address signals can be transmitted simultaneously, but layout flexibility decreases and congestion increases
Solution Approach 1:
The patent employs periodic transmission of address signals through time-division multiplexing. Row addresses and column addresses are transmitted alternately on the shared bus during different time periods, controlled by timing signals. This periodic action maintains full address transmission capacity while using fewer physical signal lines, thereby improving layout flexibility.
3Ease of operation
If separate address buses are used for row and column addresses, then address decoding can be performed independently, but the number of signal lines and device complexity increase
Solution Approach 1:
The patent introduces intermediary components including a multiplexer in the central logic region and demultiplexers in bank logic regions as mediators between the shared bus and address decoders. These intermediaries manage the time-multiplexed signals, separating row and column addresses for independent decoding while using a shared physical bus, thus reducing signal line count without compromising independent address decoding capability.
Data Source
AI summary
Apparatuses and methods for shared row and column address buses. Row and column addresses are distributed along separate respective global buses in a central logic region of a memory. The row and column addresses are coupled through a shared address bus from the central logic region to a bank logic region. For example the row address may be provided along the shared address bus at a first time and the column address may be provided along the shared address bus at a second time.