Shared Address Path for Memory Bank Refresh and Access
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining refresh operations of memory banks while allowing access to other banks, particularly in adhering to manufacturer specifications regarding the number of refresh operations before transitioning between modes, which can lead to memory leakage and data loss if specifications are violated.
Innovation Solution
The implementation of a shared address path mechanism that allows for simultaneous refresh and access operations by using even and odd bank control blocks, incrementing row addresses internally to ensure correct refresh and access operations without violating manufacturer-specified refresh cycles, thereby preventing memory leakage and data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory bank is refreshed using a single address path, then the refresh operation can be completed, but the memory bank cannot be accessed during the refresh cycle and the address path is blocked for other operations
Solution Approach 1:
The memory system is divided into multiple memory banks (first memory bank, second memory bank) that can operate independently. The address path is segmented to allow simultaneous refresh operations on one bank while access operations occur on another bank, eliminating the blocking effect and maintaining both refresh reliability and access productivity
Solution Approach 2:
A row address register acts as an intermediary component that receives and holds row addresses for both refresh and access operations. This intermediary allows the address path to be shared between refresh and access operations by properly managing address registration timing, enabling simultaneous operations without conflict
2Reliability
If refresh operations are performed frequently to prevent memory leakage, then data integrity is maintained, but the frequency of access operations to other memory banks is reduced
Solution Approach 1:
Multiple memory banks are segmented to allow parallel operations. While one bank undergoes refresh operations, other banks remain available for access operations, maintaining both data integrity through frequent refreshes and access productivity through simultaneous operations on different banks
Solution Approach 2:
The system maintains continuous useful action by ensuring that while one memory bank is being refreshed, other memory banks continue to serve access requests. This continuity ensures that data integrity is maintained through ongoing refresh operations while access productivity is sustained through simultaneous access operations on other banks
3Reliability
If manufacturer-specified refresh cycles are strictly followed, then memory leakage is prevented, but the flexibility to optimize access operations is reduced
Solution Approach 1:
Memory banks are segmented to operate independently with dedicated control blocks. This segmentation allows the system to strictly follow manufacturer-specified refresh cycles for each bank while simultaneously optimizing access operations on other banks, maintaining both refresh compliance and access flexibility
Solution Approach 2:
The system dynamically manages address registration and bank selection based on operation type. The row address register and control blocks dynamically switch between refresh and access modes, allowing strict adherence to refresh cycles while maintaining flexibility to optimize access operations based on system needs
Data Source
AI summary
A memory device includes memory banks that each has multiple rows with row addresses. The memory device also includes a counter that stores and increments a first row address of a first row of a first set of memory banks to a second row address of a second row of the first set of memory banks in response to a first refresh operation when the memory device is operating in a first mode. The memory device further includes circuitry that blocks incrementing the second row address to a third row address of a third row of the first set of memory banks when the memory device transitions from the first mode to a second mode and the first refresh operation is not paired with a second refresh operation that is performed when the memory device is operating in the first mode.