Shared Address Translation for Accelerator Memory Requests
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Solution Overview
Problem
Existing hardware accelerator implementations require separate memory management units for address translation, leading to increased software complexity and overhead, especially when handling asynchronous tasks with virtual addresses.
Innovation Solution
Reusing the memory management circuitry of the processing circuitry for address translation of accelerator-triggered memory access requests, allowing hardware accelerators to operate within the same address translation context as the processing circuitry, and implementing an asynchronous fault reporting mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate memory management units are used for hardware accelerators, then address translation can be performed independently, but software complexity and configuration overhead increase
Solution Approach 1:
The patent applies universality by enabling the processing circuitry's memory management circuitry to handle address translation for both processing circuitry memory accesses and hardware accelerator memory accesses. This multi-functional approach eliminates the need for separate memory management units in hardware accelerators, reducing software complexity while maintaining address translation capability. The memory management circuitry is configured to receive memory access requests from either source and perform translation using the same translation contexts.
2Productivity
If hardware accelerators use separate memory management, then asynchronous tasks can be handled independently, but resource utilization and processing efficiency decrease
Solution Approach 1:
The patent applies merging by combining the memory management functionality for processing circuitry and hardware accelerators into a single unified memory management circuitry. This consolidation allows asynchronous hardware accelerator tasks to be handled efficiently using shared resources including translation contexts, address translation mechanisms, and control logic, thereby improving resource utilization while maintaining independent asynchronous task handling capability.
3Adaptability or versatility
If multiple translation contexts are maintained for hardware accelerators, then context switching is enabled, but management overhead and software complexity increase
Solution Approach 1:
The patent applies universality by having the unified memory management circuitry maintain multiple translation contexts that can be used by both processing circuitry and hardware accelerators. The same context management mechanisms handle context switching for both sources, enabling context switching capability while reducing software management overhead through a single point of control rather than separate management systems.
Data Source
AI summary
An apparatus comprises processing circuitry to execute instructions; memory management circuitry associated with the processing circuitry, to perform address translation in response to memory access instructions executed by the processing circuitry; and accelerator control interface circuitry to exchange control signals with at least one hardware accelerator configurable, based on instructions executed by the processing circuitry, to perform a delegated task. The memory management circuitry is configured to maintain a plurality of active translation contexts of a given translation regime, each active translation context being defined by context information stored in a corresponding set of context control registers; and the apparatus further comprises context fault generating circuitry to generate a context fault indication in response to an accelerator-triggered memory access request from a given hardware accelerator and associated with a translation context other than one of the plurality of active translation contexts.