Shared AES SBox Circuitry for Lower-Complexity Encryption Hardware
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional hardware security systems require significant resources and space to implement both substitution boxes (SBoxes) and inverse SBoxes for AES encryption, leading to increased complexity, power consumption, and reduced throughput due to the need for separate hardware components and complex mathematical computations.
Innovation Solution
The implementation of a combined SBox and inverse SBox in VHDL hardware circuitry that dynamically generates multiplicative inverse values using a Quine-McCluskey algorithm, reducing the need for separate components and complex calculations by reusing resources and sharing circuitry for both encryption and decryption processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate hardware components are used for SBox and inverse SBox in AES encryption, then encryption and decryption functionality is achieved, but hardware complexity and space requirements increase significantly
Solution Approach 1:
The patent combines the SBox and inverse SBox into a single hardware component that can perform both encryption and decryption functions. The shared hardware circuitry includes a single 8x1 multiplexer and electrical components that are configured to execute both SBox substitution for encryption and inverse SBox substitution for decryption, eliminating the need for separate dedicated hardware for each function.
Solution Approach 2:
The hardware circuitry is designed as a universal component capable of performing multiple functions - specifically, it can function as both an SBox for encryption and an inverse SBox for decryption. The same electrical components and multiplexer structure are reused for both encryption and decryption operations, making the hardware multi-functional rather than requiring separate specialized components.
2Reliability
If separate hardware components are used for SBox and inverse SBox, then complete AES encryption capability is provided, but integrated circuit size increases by approximately 50%
Solution Approach 1:
The patent merges the SBox and inverse SBox into a single integrated circuit component, reducing the overall area occupied. By sharing the multiplexer and electrical components between encryption and decryption functions, the physical space required for implementing AES capability is reduced by approximately 50% compared to using separate dedicated hardware components.
3Reliability
If complex mathematical computations are performed using separate SBox and inverse SBox components, then AES encryption standards are met, but power consumption increases
Solution Approach 1:
The shared hardware circuitry performs both encryption and decryption computations using the same electrical components and multiplexer structure. This universality reduces redundant computational operations and power consumption, as the same hardware resources are reused rather than requiring separate power-intensive computational paths for each encryption/decryption function.
4Reliability
If separate SBox and inverse SBox components are implemented, then encryption and decryption can be performed, but throughput is reduced due to increased processing complexity
Solution Approach 1:
By combining SBox and inverse SBox into a single hardware unit with shared components, the patent reduces the number of processing stages and data transfer steps required. The merged architecture allows encryption and decryption to be performed more efficiently within the same circuit, increasing throughput compared to separate components that would require additional processing overhead.
Data Source
AI summary
Hardware circuitry defines logic for both Sbox generation and inverse Sbox generation via generating a multiplicative inverse matrix as a truth table for data. The hardware circuitry receives input plain text to be encrypted. The hardware circuitry divides the input plain text to be encrypted. The hardware circuitry feeds multiplicative inverse values generated from the input plain text to a transformer module for performing affine to encrypt the plain text data. The hardware circuitry receives encrypted data to be decrypted. The hardware circuitry divides the encrypted data to be decrypted. The hardware circuitry feeds multiplicative inverse generated from the encrypted data to the transformer module for performing inverse affine to decrypt the encrypted data.