Shared Sense Amplifier Memory Layout for Shorter 3D Bit Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in reducing current consumption and circuit area while maintaining high integration and capacity, particularly in three-dimensional memory structures.
Innovation Solution
The memory device incorporates a configuration where a first memory cell and a second memory cell share a sense amplifier unit, with bit lines connecting these memory cells to the sense amplifier unit, allowing for efficient operation and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory device uses a three-dimensional memory structure for high integration and capacity, then storage capacity is improved, but current consumption increases due to longer bit line lengths
Solution Approach 1:
The bit line is divided into multiple segments with different lengths, where each segment serves a specific memory cell group. This segmentation allows shorter bit line segments to charge/discharge faster, reducing the overall charging time and current consumption while maintaining high storage capacity through the three-dimensional structure.
Solution Approach 2:
Different bit line segments are designed with different lengths according to their specific functional requirements and positional characteristics in the three-dimensional memory structure. This local optimization ensures that each bit line segment has appropriate charging characteristics for its location, reducing overall current consumption while maintaining high integration.
2Productivity
If the bit line length is increased to connect more memory cells, then circuit integration is improved, but parasitic capacitance increases
Solution Approach 1:
The bit line is segmented into multiple sections with different lengths, where each segment serves a specific memory cell group. This segmentation limits the maximum length of any single bit line segment, thereby controlling parasitic capacitance while maintaining high circuit integration through the three-dimensional arrangement.
Solution Approach 2:
The patent utilizes a three-dimensional memory structure where bit lines are arranged in multiple layers and directions. This dimensional change allows memory cells to be connected through spatial distribution rather than solely through extended planar bit lines, reducing parasitic capacitance while maintaining high integration.
3Adaptability or versatility
If separate chips are used for memory structure and peripheral circuit, then manufacturing flexibility is improved, but device complexity increases due to bonding requirements
Solution Approach 1:
The patent integrates the memory cell array and peripheral circuits (including sense amplifier units) into a single chip structure. This merging eliminates the need for complex bonding processes between separate chips, reducing device complexity while maintaining manufacturing flexibility through unified fabrication processes.
Solution Approach 2:
The single chip structure is designed to perform multiple functions, including memory storage, sensing, and control operations, all integrated on one substrate. This multi-functionality approach reduces the need for separate specialized chips and their associated bonding complexity, while maintaining adaptability through unified design.
Data Source
AI summary
A memory device includes a first memory cell and a second memory cell each corresponding to a first column address, a first sense amplifier unit, a first bit line connected between the first memory cell and the first sense amplifier unit, and a second bit line connected between the second memory cell and the first sense amplifier unit.