Shared Amplifier Circuitry for Memory Array Power Reduction
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Solution Overview
Problem
The challenge in reducing the size and power consumption of memory devices while maintaining storage capacity is that increasing memory array density increases bit line and source line length, leading to higher power consumption, and decreasing density increases the number of arrays, resulting in larger device sizes due to replicated circuitry.
Innovation Solution
Configuring memory arrays to share PMOS-follower and preamplifier circuitry, with circuitry positioned at both ends of the arrays and pairs of arrays sharing common circuitry, to reduce the effective length of bit and source lines and minimize replicated components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory array density is increased, then storage capacity is improved, but bit line and source line length increases leading to higher power consumption
Solution Approach 1:
The memory device is divided into multiple memory arrays, each with its own dedicated bit lines and source lines. By segmenting the memory into separate arrays rather than using a single large array, the bit line and source line lengths are reduced while maintaining total storage capacity, thereby reducing power consumption associated with long interconnect lines.
2Quantity of substance
If memory array density is increased, then storage capacity is improved, but device size increases due to replicated circuitry
Solution Approach 1:
Multiple memory arrays share common amplifier circuitry and control logic. By merging these supporting circuits into shared resources rather than replicating them for each array, the overall device area is reduced while maintaining the storage capacity benefits of multiple arrays.
3Use of energy by moving object
If bit line and source line length is reduced, then power consumption is reduced, but storage capacity decreases
Solution Approach 1:
The memory device utilizes a two-dimensional array configuration where multiple smaller arrays are arranged in a planar layout. This dimensional arrangement allows short bit and source lines within each array while achieving large total storage capacity through the combined area of multiple arrays, effectively decoupling line length from total capacity.
Data Source
AI summary
In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.