Shared Antifuse Structure for OTP Memory Cell Isolation
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Solution Overview
Problem
Non-volatile memory (NVM) with one-time programmable (OTP) cells faces challenges in layout area efficiency due to the use of shallow trench isolation (STI) structures, which occupy significant space and limit the effective layout area for OTP memory cells.
Innovation Solution
The implementation of a non-volatile memory structure that includes fin field effect transistors (FinFETs), an antifuse structure, and a single diffusion break (SDB) isolation structure, where the antifuse structure is shared between two OTP memory cells, allowing for the omission of STI structures and increasing the effective layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trench isolation (STI) structures are used to isolate adjacent OTP memory cells, then isolation between cells is achieved, but the layout area occupied by STI structures increases, reducing the effective layout area for OTP memory cells
Solution Approach 1:
The patent merges the isolation function with the antifuse structure by having the antifuse structure serve dual purposes: as the programmable element and as the isolation structure between adjacent OTP memory cells. This eliminates the need for separate STI structures, thereby reducing the layout area while maintaining cell isolation.
Solution Approach 2:
The antifuse structure is designed to perform multiple functions simultaneously: it acts as the one-time programmable element for data storage and as the isolation structure separating adjacent memory cells. This multi-functionality reduces the overall device complexity and layout area.
2Reliability
If STI structures are used for isolating OTP memory cells, then proper isolation is provided, but the packing density of memory cells is reduced due to the space occupied by STI structures
Solution Approach 1:
The isolation function is merged into the antifuse structure itself, eliminating the need for additional STI structures. This integration increases the packing density by removing redundant isolation elements while maintaining proper cell isolation through the antifuse structure's inherent design.
3Area of stationary object
If a sharing gate structure is used in the antifuse structure, then the layout area is further reduced, but the manufacturing complexity increases
Solution Approach 1:
The sharing gate structure merges the gate functions of multiple antifuse elements into a single shared gate, reducing the layout area. While this increases structural complexity, the complexity is managed through systematic design patterns that allow for scalable implementation.
Solution Approach 2:
The sharing gate serves multiple antifuse elements simultaneously, performing the gate function for multiple memory cells with a single structure. This multi-functionality reduces the overall layout area while the systematic design approach keeps manufacturing complexity manageable.
Data Source
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AI summary
A non-volatile memory (100) includes a fin structure (140), a first FinFET (210), a second FinFET (220), an antifuse structure (300), a third FinFET (230), and a fourth FinFET (240). The antifuse structure (300) is formed on the fin structure (140) and has a sharing gate (GA), an SDB isolation structure (134), a first source/drain region (SA), and a second source/drain region (SB). The SDB isolation structure (134) isolates the first source/drain region (SA) and the second source/drain region (SB). The first FinFET (210), the second FinFET (220) and a first antifuse element (310) compose a first OTP memory cell (110), and the third FinFET (230), the fourth FinFET (240) and a second antifuse element (320) compose a second OTP memory cell (120). The first OTP memory cell (110) and the second OTP memory cell (120) share the antifuse structure (300).