Shared Arithmetic Unit Allocation for DLA and Vector Processors
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Solution Overview
Problem
Traditional SoC designs face challenges in dynamically allocating arithmetic units between deep learning accelerators (DLA) and vector processors (VP) to meet varying computing needs, leading to inefficiencies in power consumption and circuit area usage.
Innovation Solution
A computing device with a resource allocation manager dynamically allocates arithmetic units to DLA and VP based on their respective calculation demands, using an operator to perform calculations with specific groups of units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of arithmetic units is determined at chip design and production time, then the hardware computing power is fixed, but this leads to waste of circuit area when computing needs vary
Solution Approach 1:
The patent implements dynamic allocation of arithmetic units between DLA and VP through a resource allocation manager that can reconfigure the operator structure at runtime based on computing needs, transforming the static hardware architecture into a dynamic one that adapts to varying workloads
Solution Approach 2:
The operator is designed with arithmetic units that can serve multiple purposes - functioning as part of DLA for deep learning computations or as part of VP for vector processing tasks, allowing the same hardware resources to fulfill multiple functions based on demand
2Reliability
If DLA and VP are designed with independent hardware architectures, then each can perform its specific computations, but this leads to waste of circuit area
Solution Approach 1:
The patent merges the arithmetic units of DLA and VP into a shared operator pool, where arithmetic units are no longer dedicated to a single processor but are shared between both DLA and VP through a resource allocation manager that dynamically assigns them based on computational needs
Solution Approach 2:
The arithmetic units in the operator are designed to be universal, capable of performing both deep learning computations and vector processing operations, eliminating the need for separate dedicated hardware for each function
3Productivity
If arithmetic units are statically allocated to DLA and VP, then resource allocation is simple, but this leads to inefficiency in power consumption and circuit area usage
Solution Approach 1:
The resource allocation manager dynamically adjusts the allocation of arithmetic units between DLA and VP based on real-time computing demands, allowing the system to optimize power consumption by activating only the necessary number of arithmetic units for current tasks rather than keeping all units continuously powered
Solution Approach 2:
The system changes operational parameters by dynamically adjusting the number and configuration of active arithmetic units based on workload characteristics, enabling efficient power management through parameter optimization rather than static configuration
Data Source
AI summary
A computing device, an operation method of the computing device, and a system on chip are provided. The computing device includes an operator and a resource allocation manager. The operator includes multiple arithmetic units. The resource allocation manager is coupled to the operator and allocates the arithmetic units to a deep learning accelerator and a vector processor for use according to an amount of calculation of the deep learning accelerator and an amount of calculation of the vector processor. The operator receives a first operation request and a second operation request from the deep learning accelerator and the vector processor respectively, uses a first arithmetic unit group of the arithmetic units to perform a calculation of the first operation request, and uses a second arithmetic unit group of the arithmetic units to perform a calculation of the second operation request according to an allocation result.