Shared Array BIST Addressing for IC Memory Testing
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Solution Overview
Problem
Existing methods for testing integrated circuits with parallel array BIST test methods require significant chip area and prolong test time due to complex comparison circuits and sequential testing of memories, necessitating a more efficient approach to minimize test time and circuit area without complicated software control or customized designs.
Innovation Solution
The method involves polling memories to determine shared comparison trees, mapping a shared BIST address space, estimating completion time based on maximum total memory size, and reconfiguring BIST circuitry to accommodate this, allowing for efficient testing of multiple memories using a single implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parallel array BIST test methods are used to achieve highest quality memory test, then test quality is improved, but chip area increases
Solution Approach 1:
Multiple BIO macros are merged into a single shared comparison tree structure. The patent implements this by having multiple memory blocks share a common BIST engine and comparison logic, thereby reducing the total chip area required while maintaining comprehensive testing capability across all memory blocks.
Solution Approach 2:
The shared comparison tree serves multiple memory blocks simultaneously. The BIST engine is designed to universally test different memory blocks by dynamically configuring the test address space, allowing a single comparison tree to perform quality testing for multiple memory blocks without requiring separate dedicated comparison circuits for each.
2Area of stationary object
If comparison trees are shared across multiple memories to reduce area, then chip area is reduced, but test time increases due to sequential testing
Solution Approach 1:
The BIST engine dynamically reconfigures the test address space based on which memory block is currently being tested. The system automatically adjusts the test configuration and address mapping for each memory block, enabling efficient sequential testing without wasted time. The dynamic reconfiguration ensures that each memory block is tested optimally using the shared comparison tree.
Solution Approach 2:
The system incorporates feedback mechanisms to automatically determine the test completion status for each memory block. The BIST engine monitors test results and uses this feedback to manage the sequential testing process, ensuring that each memory block is fully tested before moving to the next one, thereby minimizing overall test time while maintaining comprehensive coverage.
3Loss of time
If BIST circuitry is reconfigured to match actual memory configuration, then test time is reduced, but device complexity increases
Solution Approach 1:
The BIST engine performs self-configuration by automatically detecting the actual memory configuration and adjusting the test address space accordingly. The system autonomously determines which memory blocks are present and configures the comparison tree to match the actual hardware setup, eliminating the need for external complex reconfiguration logic and reducing overall device complexity.
Solution Approach 2:
The system changes key parameters such as the test address space mapping and comparison tree configuration based on the detected memory configuration. By dynamically adjusting these parameters, the BIST engine adapts to different memory setups without requiring physical circuit changes or complex reconfiguration logic, thereby reducing device complexity while optimizing test time.
Data Source
AI summary
A method for testing integrated circuits (ICs) by automatically extending addressing for shared array built-in self-test (BIST) circuitry, includes polling a plurality of memories to determine which of the plurality of memories are sharing a first comparison tree and mapping a shared array BIST address space to each of the plurality of memories using the first comparison tree. Additionally, the method includes estimating a shared array BIST completion time corresponding to a most significant bits of a maximum total memory address size under test, reconfiguring the shared array BIST circuitry to accommodate the estimated shared array BIST completion time and testing the plurality of memories sharing the first comparison tree.