SoC Architecture Generation via Shared Array Resource Optimization
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Solution Overview
Problem
The existing methods for SoC architecture design face challenges in optimizing module division, leading to suboptimal performance and potential rework, as they rely heavily on designer experience and do not effectively manage array usage across processes, which can result in exceeding chip area and performance constraints.
Innovation Solution
An architecture generating device that identifies declaration statements for arrays across multiple processes and generates a hardware specification file by replacing them with shared arrays, allowing for efficient resource sharing and optimizing hardware specification generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple separate arrays are used for different processes, then each process can operate independently, but the chip area increases and resource efficiency decreases
Solution Approach 1:
The patent merges multiple separate arrays that are used by different processes into a single shared array. The declaration statement identifying unit detects arrays declared in different processes, and the specification generating unit replaces them with a shared array that multiple processes can access, thereby reducing total memory usage while maintaining process independence
Solution Approach 2:
The patent creates a universal shared array that serves multiple processes simultaneously. Instead of dedicating separate arrays to each process, a single array structure is designed to be accessed by multiple processes through controlled interfaces, making the memory resource multi-functional and reducing overall chip area requirements
2Adaptability or versatility
If module division is conducted based on designer experience, then design flexibility is maintained, but optimal performance cannot be guaranteed and rework increases
Solution Approach 1:
The patent implements an automated feedback mechanism where the declaration statement identifying unit analyzes the hardware specification file, identifies arrays used across multiple processes, and the specification generating unit automatically generates optimized module divisions. This closed-loop approach provides feedback on resource usage patterns and automatically adjusts the architecture to achieve optimal performance while maintaining design flexibility
Solution Approach 2:
The patent enables the design system to self-optimize by automatically analyzing the hardware specification, identifying optimization opportunities in array usage, and generating optimized module divisions without requiring manual intervention. The system serves itself by detecting and correcting suboptimal architecture decisions, reducing rework while maintaining flexibility
3Area of stationary object
If arrays are shared across multiple processes, then chip area is reduced and resource efficiency improves, but array access management becomes more complex
Solution Approach 1:
The patent introduces an intermediary shared array structure with controlled access mechanisms. The declaration statement identifying unit detects arrays used by multiple processes, and the specification generating unit creates a shared array with defined access protocols. This intermediary structure manages the complexity of simultaneous access by providing a standardized interface that multiple processes can use without direct conflict
Data Source
AI summary
A specification editing unit edits a hardware specification file in order to replace a plurality of arrays used in a plurality of processes with a shared array. If a post-edit hardware specification file does not satisfy constraint, a specification transforming unit transforms the hardware specification file so that the plurality of processes are executed in a parallel manner. An architecture generating unit generates an architecture file expressing an architecture of an SoC (System On Chip) having hardware corresponding to the hardware specification file.