Shared Balance Operators for Reconfigurable Cryptographic Loop Mapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing reconfigurable computing technologies face challenges in mapping cryptographic algorithms, particularly in loop computation, with high personnel requirements, long mapping times, poor loop communication, and suboptimal pipeline performance, lacking a satisfactory solution for automatic mapping.
Innovation Solution
A loop array mapping method using a shared balance node operator is implemented, optimizing the mapping graph by minimizing the minimum iteration interval (MII) through shared balance node operators and utilizing a storage data unit (SREG) for data transfer, especially in multi-fan-out operators and loop bodies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manual mapping methods are used for cryptographic algorithms on reconfigurable processors, then mapping flexibility is maintained, but mapping time increases and pipeline performance deteriorates
Solution Approach 1:
The patent implements automatic mapping technology that enables the reconfigurable processor to perform mapping operations autonomously without manual intervention. The system uses automated algorithms to analyze cryptographic algorithm characteristics and generate optimal mapping configurations, thereby eliminating the time-consuming manual mapping process while maintaining adaptability through programmable mapping rules.
Solution Approach 2:
The patent optimizes mapping parameters such as iteration interval and resource allocation dynamically based on the specific cryptographic algorithm being implemented. By adjusting these parameters automatically, the system achieves both fast mapping and high pipeline performance, resolving the contradiction between mapping speed and performance optimization.
2Ease of manufacture
If conventional mapping methods are used for loop bodies in cryptographic algorithms, then implementation simplicity is maintained, but loop communication efficiency deteriorates and pipeline performance decreases
Solution Approach 1:
The patent segments the loop body mapping into distinct phases: data dependency analysis, resource allocation, and iteration interval optimization. Each phase is handled by specialized sub-routines that work together to achieve high pipeline performance while maintaining implementation simplicity through modular design.
Solution Approach 2:
The patent performs preliminary analysis of data dependencies and resource requirements before generating the actual mapping configuration. This pre-computation step identifies optimal iteration intervals and resource allocation strategies in advance, enabling efficient loop communication and high pipeline performance without complicating the implementation.
3Manufacturing precision
If more resources are allocated to improve mapping quality, then mapping effect improves, but area consumption and power consumption increase
Solution Approach 1:
The patent designs a universal mapping framework that can handle different cryptographic algorithms using the same resource pool. The system dynamically allocates resources based on the specific algorithm requirements, allowing one set of resources to serve multiple functions and algorithms, thereby improving mapping quality without proportionally increasing area consumption.
Solution Approach 2:
The patent implements selective resource allocation that applies optimization only to critical path operations and data dependencies that genuinely require additional resources. Non-critical operations use shared or reduced resources, achieving good mapping quality without excessive area consumption across the entire system.
Data Source
AI summary
A loop array mapping method of a shared balance operator is based on a reconfigurable cryptographic algorithm. The mapping graph is optimized by adopting a balance node operator mode, so that the mapping graph has a smallest iteration interval and a largest pipeline performance, thus solving a problem of poor pipeline performance of manual configuration and saving a great deal of human and mental labor, without adding the balance operator node manually by manual computing. In the present disclosure, a shared balance node operator solution is adopted to process a balance node of the multi-fan-out operator, so that computation resources are minimized and performance is maximized. The storage data unit SREG is used for data transfer and communication, which solves a problem that communication of data between loop bodies occupies more transfer operator resources, saves a lot of hardware resources and further improves pipeline performance.