Shared Bank Select Transistors for Compact Memory Layout

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Solution Overview

Problem

Existing memory bank architectures in fluid ejection devices, such as print heads, require multiple transistors for selecting memory units, leading to space constraints and inefficiencies in data storage.

Innovation Solution

Implementing a common bank select transistor for a plurality of memory units within a memory bank, reducing the number of transistors needed and optimizing space usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If multiple transistors are used for selecting memory units in a memory bank, then the memory selection functionality is achieved, but the space consumption increases and the number of transistors increases

Engineering Contradiction:

Improvenumber of transistorsVSAvoidspace consumption

Core Design Contradiction:

Device complexityVSArea of stationary object

Solution Approach 1:

The patent combines multiple transistors into a single shared transistor that serves multiple memory units within a memory bank. This bank select transistor is shared across multiple memory units, eliminating the need for separate select transistors for each unit, thereby reducing both the transistor count and the space required for memory bank architecture.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The bank select transistor is designed to perform multiple functions by being shared across multiple memory units. A single transistor controls access to multiple memory units through coordinated operation with row and column select transistors, making the transistor universal rather than dedicated to a single memory unit.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Area of stationary object

If a common bank select transistor is shared across multiple memory units, then the space consumption and transistor count are reduced, but the complexity of memory unit selection control increases

Engineering Contradiction:

Improvespace consumptionVSAvoidselection control complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The memory bank architecture is segmented into hierarchical levels of selection control. The bank select transistor operates at the bank level, while row and column select transistors operate at the unit level within each bank. This segmentation allows the common transistor to control multiple units through coordinated multi-level selection signals, managing complexity through structured hierarchy.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediary control mechanisms including row and column select transistors that mediate between the common bank select transistor and individual memory units. These intermediary transistors translate the shared bank-level control signal into unit-specific access control, managing the complexity of sharing a single transistor across multiple units.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentEP4147874B1Accessing memory units in a memory bank

Publication Date: 2025.08.27 HEWLETT PACKARD DEVELOPMENT COMPANY LP

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AI summary

A first bank select transistor is common to a first plurality of memory units in a first memory bank. A second bank select transistor is common to a second plurality of memory units in a second memory bank. The first and second bank select transistors facilitate accessing a memory unit of the respective plurality of memory units based on a bank select signal.