Shared BCH Error Correction for Multi-Channel Data Storage
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Solution Overview
Problem
Data storage devices face challenges in achieving high throughput and accurate error correction while minimizing data errors, as existing solutions often require intensive error correction calculations to be performed locally, which can impact performance.
Innovation Solution
A shared corrector module using an error correction algorithm, such as the Bose Chauduri Hocquenghem (BCH) algorithm, is implemented to detect errors locally and perform intensive correction calculations, generating correction solutions that are then applied locally at channel controllers, optimizing error correction processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction calculations are performed locally at each memory device, then error correction accuracy is improved, but device complexity and processing overhead increase
Solution Approach 1:
The patent extracts the intensive error correction calculation functionality from individual memory devices and concentrates it in a separate corrector module. The memory devices perform only lightweight error detection and data transmission, while the corrector module handles the computationally intensive BCH error correction calculations, thereby reducing device complexity at memory locations while maintaining correction accuracy.
Solution Approach 2:
The corrector module acts as an intermediary between the memory devices and the host system. It receives data and error detection information from memory devices, performs the intensive error correction calculations using BCH algorithms, and returns corrected data to the host, thereby mediating the complex error correction process without burdening the memory devices themselves.
2Productivity
If more commands are processed to increase throughput, then productivity is improved, but error detection and correction time may increase
Solution Approach 1:
The error correction process is segmented into distinct phases: error detection at memory devices (lightweight), data transmission to corrector module, intensive error correction calculation at the corrector module, and result return. This segmentation allows parallel processing of multiple commands at different stages, improving overall throughput while maintaining timely error correction.
Solution Approach 2:
Memory devices perform self-service error detection using embedded error detection codes, identifying errors locally without requiring intensive processing at this stage. This allows rapid error identification and enables the system to proceed with parallel command processing while only requiring correction intervention when actually needed.
Data Source
AI summary
An apparatus for error correction for a data storage device may include an input interface that is configured to receive individual error correction requests to correct data from multiple channel controllers and that is configured to receive error correction information corresponding to the error correction requests, where each of the channel controllers is arranged and configured to control operations associated with one or more memory chips. The apparatus may include a corrector module that is operably coupled to the input interface and that is arranged and configured to perform error correction using an error correction algorithm and the error correction information to generate correction solutions, where the corrector module is a shared resource for the multiple channel controllers. The apparatus may include an output interface that is operably coupled to the corrector module and that is arranged and configured to communicate the correction solutions to the channel controllers.