Shared Bias Device for Plate Line Drivers

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Solution Overview

Problem

Conventional memory devices face challenges in efficiently managing the voltage slew rate between plate lines and data lines due to differences in resistance-capacitance (RC) products, leading to undesired routing and power consumption issues as the number of subarrays and plate line drivers increases.

Innovation Solution

Implementing a multilevel decoding architecture for plate select lines and plate line drivers, which reduces the number of routing plate select lines by half, and using a shared bias device or diodes to manage voltage across multiple plate line drivers, ensuring robust current supply and minimizing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of subarrays and plate line drivers increases, then the capacity of memory devices is improved, but the routing complexity and power consumption increase

Engineering Contradiction:
ImprovecapacityVSAvoidrouting complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

Multiple plate line drivers share a common bias device, merging the biasing function into a single resource that serves all drivers. This reduces the total number of components and routing paths required, thereby reducing routing complexity while maintaining the ability to drive multiple subarrays simultaneously

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared bias device performs the biasing function for multiple plate line drivers universally, making a single component serve multiple purposes. This multi-functionality reduces the overall device complexity and number of routing paths needed compared to having dedicated bias devices for each plate line driver

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If the number of plate line drivers increases, then the capacity of memory devices is improved, but the power consumption increases

Engineering Contradiction:
ImprovecapacityVSAvoidpower consumption
Core Design Contradiction:
Quantity of substanceVSLoss of energy

Solution Approach 1:

By merging multiple bias devices into a single shared bias device, the overall power consumption is reduced. The shared device can be optimized to provide bias current efficiently to multiple plate line drivers simultaneously, avoiding the redundant power consumption that would occur with separate bias devices for each driver

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The universal bias device serves multiple plate line drivers, enabling a single component to manage biasing for multiple drivers. This multi-functionality allows for more efficient power distribution and reduces total power consumption compared to having dedicated bias devices for each plate line driver

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If a shared bias device is used for multiple plate line drivers, then the device complexity is reduced, but the current supply control becomes more difficult

Engineering Contradiction:
Improvedevice complexityVSAvoidcurrent supply control
Core Design Contradiction:
Device complexityVSEase of operation

Solution Approach 1:

The shared bias device incorporates feedback mechanisms that monitor and adjust bias current based on the operational state of multiple plate line drivers. This feedback control ensures that current supply is automatically optimized for each driver without requiring complex manual control, maintaining ease of operation while reducing device complexity

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20240212734A1Plate line drivers with a shared bias device
Publication Date: 2024.06.27 MICRON TECHNOLOGY INC
  • US20240212734A1 patent drawing
  • US20240212734A1 patent drawing
  • US20240212734A1 patent drawing

AI summary

A variety of applications can include apparatus having a memory device comprising plate select lines coupled to capacitors of memory cells of the memory device, plate line drivers coupled to the plate select lines, and a bias device coupled to each plate line driver. Use of a single bias device can allow for generation of robust current across multiple plate line drivers. The plate line drivers can be arranged with different formats that can operate with a single bias device. Plate select lines and the plate line driver can be structured in a scheme to balance the number of plate select lines and device counts for the plate line drivers.