Programmable Shared BIST Architecture for Embedded Memory Testing
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Solution Overview
Problem
Conventional Built-In Self Test (BIST) architectures for integrated circuits face challenges such as large die size consumption, routing congestion, and limited sharing of test and repair resources due to hard-coded controllers and parallel connections, making at-speed testing difficult and costly, especially for complex ICs with multiple memory types.
Innovation Solution
A programmable, sharable BIST architecture with asynchronous links and a main controller that initializes local test controllers in a ring configuration, allowing for efficient clock routing and reduced power utilization, while keeping size-dependent components near memories and sharing static parts to minimize area and routing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a common controller is used to control test activities on the entire chip while supporting multiple memory types, then device versatility is improved, but device complexity increases due to routing congestion from parallel connections
Solution Approach 1:
The patent segments the BIST controller into multiple independent controllers, each dedicated to a specific memory type. This segmentation eliminates the need for a single complex common controller that would require parallel connections to all memory types, thereby reducing routing congestion while maintaining support for multiple memory types through distributed control architecture
Solution Approach 2:
Each dedicated controller is designed with universal functionality to handle its specific memory type efficiently. The controllers share common test infrastructure and can be configured to support different memory variants, achieving versatility through modular design rather than through a single complex common controller
2Adaptability or versatility
If controllers are replicated for each memory type, then adaptability is improved, but silicon area increases
Solution Approach 1:
The patent merges common test infrastructure components across multiple dedicated controllers, such as sharing test pattern generation units, comparison logic, and control signal routing. This merging reduces the total silicon area required compared to having completely separate controller implementations for each memory type, while still maintaining the benefits of dedicated control architecture
3Ease of operation
If parallel connections are used to connect all memories to a common controller, then ease of operation is improved, but area increases due to routing congestion
Solution Approach 1:
Instead of using parallel connections from a single common controller to all memories, the patent segments the control architecture into multiple dedicated controllers, each connected to its specific memory type. This eliminates the need for extensive parallel routing while maintaining ease of operation through localized control
4Reliability
If hard-coded controllers are used for each memory type, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent employs parameterizable and reconfigurable controllers that can be configured through test mode selection rather than being hard-coded for each memory type. This allows the same controller hardware to reliably execute different test algorithms by changing control parameters and test mode settings, reducing architectural complexity while maintaining test reliability
Data Source
AI summary
A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same are disclosed. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self-testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self-test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.