Shared Bit Line Structure for Memory Array Size Reduction
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Solution Overview
Problem
Device manufacturers face challenges in reducing the size of integrated circuits and semiconductor devices while increasing processing speeds and reducing power consumption, as two-dimensional memory arrays require excessive spacing and peripheral circuitry, leading to increased power consumption and reduced speed capabilities.
Innovation Solution
Implementing a shared bit line structure in memory arrays, where neighboring memory columns share bit lines and bit line bars, reducing the overall size and power consumption, and increasing processing speeds by eliminating unnecessary spacing and peripheral circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a two-dimensional memory array structure is used, then the memory array can be formed with conventional circuitry, but the spacing between memory columns increases the overall size and reduces processing speeds
Solution Approach 1:
The patent transitions from a two-dimensional memory array structure to a three-dimensional structure by forming memory columns at different heights or levels. This vertical stacking approach eliminates the need for excessive horizontal spacing between memory columns, thereby reducing the overall footprint while maintaining conventional manufacturing processes.
2Reliability
If individual bit lines are provided for each memory column, then each memory column can operate independently, but the number of bit lines and peripheral circuitry increases power consumption
Solution Approach 1:
The patent merges bit lines between adjacent memory columns by forming shared bit lines that serve multiple memory columns simultaneously. This reduction in the total number of bit lines directly decreases the power consumption associated with bit line switching and signal transmission, while memory columns remain independently operable through selective word line activation.
3Ease of manufacture
If excessive spacing is provided between memory columns, then manufacturing and assembly are simplified, but the overall size of the memory array increases
Solution Approach 1:
By stacking memory columns vertically in three dimensions, the patent reduces the horizontal spacing requirements between columns. This vertical arrangement allows memory columns to be placed closer together in the planar view, thereby reducing the overall memory array footprint while maintaining ease of manufacturing through conventional fabrication processes.
4Adaptability or versatility
If more peripheral circuitry is added to support additional bit lines, then more memory columns can be addressed, but the device complexity and power consumption increase
Solution Approach 1:
The patent combines peripheral circuitry resources by implementing shared bit lines that are collectively controlled by word line drivers. This merging approach allows multiple memory columns to be addressed using fewer peripheral circuit components, thereby reducing device complexity and power consumption while maintaining the capability to address and operate individual memory columns independently.
Data Source
AI summary
A memory array includes a first column of memory cells, a second column of memory cells, a first pre-charge circuit, a second pre-charge circuit and a set of input output circuits. The first column of memory cells includes a first bit line, a first word line and a first bit line bar. The second column of memory cells includes the first bit line bar, a second word line and a second bit line. The first pre-charge circuit is coupled to the first bit line. The second pre-charge circuit is coupled to the first bit line bar. The first column of memory cells and the second column of memory cells are configured to share the first bit line bar. The first bit line and the first bit line bar are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane.