Shared Bit Line NAND String Selection for Flash Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor memory devices shrink in size to increase storage capacity and reduce space, design and process challenges arise, particularly in efficiently programming and reading multi-state flash memory cells without unwanted boosting and errors due to shared bit lines and varying channel potentials.
Innovation Solution
The proposed solution involves sharing bit lines between pairs of NAND strings, using only one drain side selection gate per NAND string with two selection signals, and maintaining channels at a fixed potential during read and verify operations to prevent unwanted boosting and ensure accurate data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of bit lines is reduced by sharing between NAND strings, then area is reduced, but channel potential varies causing unwanted boosting and read errors
Solution Approach 1:
The bit line sharing is segmented by time - only one NAND string per bit line is active during any given read operation. Selection signals activate specific drain side selection gates to enable only the intended NAND string, while other NAND strings on the same bit line remain inactive. This temporal segmentation prevents channel potential interference between different NAND strings sharing the same bit line.
Solution Approach 2:
Drain side selection gates serve as intermediary components between the bit lines and the NAND strings. These selection gates control the connection between shared bit lines and individual NAND strings, enabling selective activation. By using these intermediary gates, the patent achieves both bit line sharing for area reduction and precise control for preventing unwanted boosting effects.
2Adaptability or versatility
If drain side selection gates are used to select NAND strings, then selectivity is improved, but channel potential is not maintained causing unwanted boosting
Solution Approach 1:
During read operations, the patent maintains all channels at the same potential (typically ground or source line potential) by keeping drain side selection gates inactive for unselected NAND strings. This equipotential condition prevents voltage differentials that would cause unwanted electron injection into floating gates. The selection signals are carefully timed and leveled to ensure no potential differences exist between active and inactive channels during the read process.
3Quantity of substance
If process geometries are shrunk to increase capacity, then storage density is improved, but design and process challenges increase
Solution Approach 1:
The patent merges multiple NAND strings onto shared bit lines, reducing the total number of bit lines required. This merging approach increases storage density by allowing more memory cells to be packed into the same area. The complexity is managed through systematic selection signaling that activates only the required NAND string during each operation, making the design scalable despite the increased number of shared resources.
Data Source
AI summary
A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential.