Shared Bit Line STT MRAM Array Density and Resistance
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Solution Overview
Problem
Conventional STT-MRAM designs face limitations in column spacing due to thermal budget constraints and BEOL compatibility, leading to increased magnetic resistance ratio decrease and switching current, which affects the performance of STT magnetic memory elements.
Innovation Solution
The implementation of a shared bit line/compressed pitch STT MRAM array, where shared bit lines are coupled to the top electrodes of multiple columns, and source lines are switchably connected to the bottom electrodes through selectively enabled transistors, allowing for concurrent access voltage application and selective complementary voltage coupling to individual STT magnetic memory elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional STT-MRAM designs use separate bit lines for each column, then column spacing can be maintained, but MTJ array density is reduced and parasitic resistance increases
Solution Approach 1:
The patent merges multiple bit lines into a single shared bit line that serves multiple columns simultaneously. The shared bit line is coupled to top electrodes of STT magnetic memory elements from multiple columns, allowing concurrent access to multiple columns while reducing the total number of bit lines, thereby increasing MTJ array density and reducing parasitic resistance.
Solution Approach 2:
The patent segments the bit line function by introducing selectively enabled transistors at each column intersection. These transistors act as switches that segment the shared bit line into column-specific access paths, enabling individual column selection while maintaining the shared infrastructure. This segmentation allows the system to achieve both high density and selective access capability.
2Temperature
If column spacing is increased to meet thermal budget constraints, then BEOL compatibility is improved, but magnetic resistance ratio decreases and switching current increases
Solution Approach 1:
The patent transitions from a planar bit line arrangement to a three-dimensional structure by overlaying the shared bit line in a upper metallization layer above the MTJ array. This vertical dimensionality change allows columns to be spaced closer together while maintaining thermal budget compliance, as the shared bit line approach reduces the number of interconnect layers and associated thermal loads.
3Object-generated harmful factors
If shared bit lines are used to increase density, then parasitic resistance is reduced, but individual element access complexity increases
Solution Approach 1:
The patent introduces selectively enabled transistors as intermediary elements between the shared bit line and individual column groups. These transistors act as mediators that control current flow to specific columns based on decode signals, simplifying the access control logic while maintaining the benefits of the shared bit line structure. The transistors isolate column groups and enable precise addressing without requiring complex control circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases MTJ array density, reduces parasitic resistance, improves the magnetic resistance ratio, and decreases switching current, enabling high-performance differential sensing and addressing the thermal budget constraints.
Implementation Method 1
The spin-transfer torque (STT) magnetic memory is one known technology for magnetic memory. The STT magnetic memory generally has an addressable array of STT bitcells, each STT bitcell having an STT magnetic memory element that includes a 'free' magnetization layer that is switchable between two stable, mutually opposite magnetization states.
Implementation Method 2
The electrical resistance of the STT magnetic memory element is lower in the P state than in the AP state, which enables reading that state.
Data Source
AI summary
An STT magnetic memory includes adjacent columns of STT magnetic memory elements having a top electrode and a bottom electrode. A shared bit line is coupled to the top electrode of the STT magnetic memory elements in at least two of the adjacent columns. The bottom electrodes of the STT magnetic memory elements of one of the adjacent columns are selectively coupled to one source line, and the bottom electrodes of the STT magnetic memory elements of another among the adjacent columns are selectively coupled to another source line.