Shared Bit Lines for Memory Cell Arrays
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Solution Overview
Problem
In advanced integrated circuit technologies with shrinking feature sizes, existing backside power rails face challenges such as routing resistance, alignment margins, layout flexibility, and packing density, particularly in FinFETs with narrow fin widths, which affect the performance and reliability of memory arrays.
Innovation Solution
The solution involves sharing bit lines and power lines between adjacent memory cells, allowing for larger metal lines that reduce resistance and capacitance, and forming these lines on the backside or frontside of the substrate to improve performance without increasing cell size, with bit lines being at least 50% wider than word lines and Vss lines shared on the backside.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit lines are made larger to reduce resistance and capacitance, then electrical performance is improved, but layout area increases
Solution Approach 1:
Adjacent memory cells share common bit lines, allowing the bit line to serve multiple cells simultaneously. This sharing approach reduces the total number of bit lines required while maintaining adequate line dimensions for acceptable resistance and capacitance values, thereby improving electrical performance without proportionally increasing layout area.
Solution Approach 2:
The bit line structure is designed to perform multiple functions: it serves as the data transmission line for multiple adjacent memory cells and simultaneously acts as a power rail in some configurations. This multi-functionality reduces the total number of separate conductors needed, improving electrical performance while controlling layout area.
2Quantity of substance
If feature sizes are shrunk to increase packing density, then more cells fit in the same area, but alignment margins are reduced and manufacturing precision becomes more difficult
Solution Approach 1:
The patent utilizes the third dimension by forming power rails on the backside of the substrate while keeping bit lines on the frontside. This vertical separation of functions allows for larger, more manufacturable feature sizes on each side while achieving high overall packing density through three-dimensional integration.
Solution Approach 2:
The memory structure is divided into frontside and backside components, with bit lines and word lines on the frontside and power rails on the backside. This segmentation allows each layer to be optimized independently for manufacturing precision while achieving high overall packing density through vertical integration.
3Adaptability or versatility
If power rails are formed on the backside to improve routing flexibility, then layout flexibility is improved, but routing resistance may increase
Solution Approach 1:
The backside power rails are designed to share conductors between adjacent memory cells, reducing the total number of power rail segments. This merging approach maintains adequate current delivery capability while improving layout flexibility through the backside routing architecture.
Data Source
AI summary
Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.