Shared Bit-Processing Circuit for Memory Redundancy Repair
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Solution Overview
Problem
Existing memory devices require a large number of circuit components, such as fuses and XNOR gates, to provide memory redundancy, which consumes significant area and reduces memory density and array efficiency.
Innovation Solution
The implementation of a memory device with shared components in the match circuit of the repair circuit, where common bit information is stored in common fuse banks and processed by a shared bit-processing circuit, reducing the number of components needed for memory redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate bit-processing circuits are used for each match sub-circuit, then each defective memory cell can be independently repaired, but the number of circuit components increases significantly
Solution Approach 1:
The patent merges the bit-processing functionality across multiple match sub-circuits by implementing a shared common bit-processing circuit. This single circuit receives common bit information from multiple fuse banks and processes it once, rather than having separate processing circuits for each match sub-circuit. The merged approach maintains the ability to repair multiple defective memory cells while significantly reducing the total number of circuit components.
Solution Approach 2:
The common bit-processing circuit is designed to serve multiple functions simultaneously - it processes bit information for multiple different defective memory cells through the multiple match sub-circuits. This universal circuit replaces what would otherwise require multiple specialized circuits, achieving both component reduction and maintained repair capability.
2Reliability
If more circuit components are used to provide memory redundancy, then more defective memory cells can be repaired, but the peripheral logic area increases
Solution Approach 1:
By merging the bit-processing functionality into a shared common circuit, the patent reduces the total area occupied by logic components. The shared circuit processes information for multiple defective cells simultaneously, eliminating the need for duplicate processing circuits and thereby reducing the peripheral logic area while maintaining full repair capability.
Solution Approach 2:
The universal bit-processing circuit performs multiple repair functions across different memory cells, replacing what would require multiple separate circuits. This multi-functional approach achieves the same level of memory redundancy with significantly reduced logic area.
3Reliability
If more circuit components are used for memory repair, then more defective cells can be repaired, but power consumption increases
Solution Approach 1:
The patent merges redundant bit-processing functions into a single shared circuit, which consumes less power than multiple separate circuits would require. The shared circuit processes bit information for multiple defective memory cells through the match sub-circuits, reducing total power consumption while maintaining the ability to repair all defective cells.
Solution Approach 2:
The universal bit-processing circuit handles repair operations for multiple memory cells, replacing multiple power-consuming circuits with a single efficient circuit that performs all necessary processing functions.
Data Source
AI summary
A memory device includes a memory cell array and a set of fuse banks including a common fuse bank storing common bit information corresponding to a plurality of defective memory cells in the memory cell array. The memory device including a plurality of match sub-circuits corresponding to respective defective memory cells of the plurality of defective memory cells. Each match sub-circuit can be configured to provide a determination of whether a memory cell address of a memory cell of the memory cell array matches an address of the respective defective memory cell. The plurality of match sub-circuit can include a shared common bit-processing circuit that is configured to receive common bit-by-bit results of a comparison between a portion of the memory cell address and the common bit information. The common bit-processing circuit can determine whether the common bit information matches the portion of the memory cell address.