Shared Bitline Failure Detection Circuit for ASIL Image Sensors
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Solution Overview
Problem
Traditional failure detection circuits for image sensors with dual bitlines require additional space and power, which is not feasible for meeting the compact and low-power demands of automotive safety integrity level (ASIL) D standards.
Innovation Solution
A failure detection circuit that includes multiple bitline inputs without requiring additional space or power, utilizing a first input node coupled to a reference voltage and an array of second input nodes, with an output stage generating a voltage indicative of any input node being lower than the reference voltage, allowing for efficient fault detection in dual-bitline image sensors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional failure detection circuits are used for each bitline in dual bitline design, then detection coverage is improved, but space consumption and power consumption increase
Solution Approach 1:
The patent combines multiple bitline monitoring functions into a single shared failure detection circuit. Instead of having separate detection circuits for each bitline, the invention uses one circuit that can monitor multiple bitlines simultaneously by multiplexing their signals through a single input node, thereby reducing the total circuit area while maintaining comprehensive failure detection coverage
Solution Approach 2:
The failure detection circuit is designed with multi-functionality to handle multiple bitlines. The circuit can selectively monitor different bitlines through a single input interface, making the detection circuit universal rather than dedicated to a single bitline. This multi-functional design allows the same circuit hardware to serve multiple monitoring purposes, reducing overall space requirements
2Reliability
If traditional failure detection circuits are used for each bitline in dual bitline design, then detection coverage is improved, but power consumption increases
Solution Approach 1:
By merging the monitoring functions for multiple bitlines into a single failure detection circuit, the patent reduces the total number of active circuit components. This consolidation means fewer transistors, amplifiers, and comparators are needed, directly reducing the overall power consumption while maintaining the ability to detect failures on all monitored bitlines
Solution Approach 2:
The universal failure detection circuit can be configured to monitor different bitlines as needed, eliminating the need for multiple dedicated circuits that would each consume power continuously. The single multi-functional circuit only needs to be active when monitoring is required, and can efficiently switch between different bitline monitoring tasks, reducing cumulative power consumption
3Reliability
If dual bitlines are used per pixel, then image quality and safety are improved, but circuit complexity increases
Solution Approach 1:
The patent applies merging by combining the failure detection functionality for multiple bitlines into a single integrated circuit block. This reduces the apparent complexity by showing that multiple monitoring functions can be achieved through one unified circuit rather than multiple separate circuits, simplifying the overall system architecture despite the dual bitline configuration
Solution Approach 2:
The failure detection circuit acts as an intermediary between the dual bitline system and the control logic. Instead of requiring complex control logic to monitor each bitline individually, the intermediary detection circuit provides a simplified interface that consolidates multiple bitline status signals, reducing the complexity of the overall control system
Data Source
AI summary
A failure detection circuit for an image sensor includes a first input node, an array of second input nodes, and an output stage. The first input node is coupled to a reference voltage. The array of second input nodes has each input node coupled to receive a signal from a bitline of a bitline array in an image sensor that includes an array of pixels with each pixel is coupled to at least one bitline of the bitline array. The output stage is coupled to generate an output voltage indicative of any of the second input nodes being lower than the reference voltage.