Shared Bitline Memory Layout for Higher Bitcell Density
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Solution Overview
Problem
Conventional memory devices face challenges such as large memory cells and low memory density, particularly in DRAM devices, due to the use of back-gated BEOL access transistors with unique drain and source electrodes for each bitcell, leading to inefficient area utilization and limited scalability.
Innovation Solution
The implementation of a memory architecture with shared drain electrodes and bit lines between adjacent memory cells, allowing for unique gating control through back-gate word lines, which reduces the area required for each bitcell and increases density without scaling the minimum feature size, achieving a 25% increase in bitcell scaling and relaxing bit line pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If unique drain and source electrodes are used for each bitcell, then transistor control is simplified, but memory cell area increases and density decreases
Solution Approach 1:
The patent merges the drain electrodes of adjacent memory cells into a shared structure. Specifically, the drain electrode of one memory cell is electrically connected to the drain electrode of another memory cell, forming a common drain electrode that serves multiple bitcells. This merging reduces the total number of drain electrodes required, thereby decreasing the area occupied by each memory cell while maintaining proper transistor control through the shared electrode structure.
2Ease of manufacture
If conventional memory cell architecture is used, then manufacturing is straightforward, but memory density is limited
Solution Approach 1:
The shared drain electrode structure serves multiple functions simultaneously: it acts as the drain electrode for multiple memory cells, provides a common electrical connection point, and reduces the overall area requirement. This multi-functional design allows the same structural element to fulfill several roles, thereby increasing memory density without significantly complicating the manufacturing process.
3Quantity of substance
If feature size is reduced to increase density, then memory density improves, but manufacturing precision requirements increase
Solution Approach 1:
Instead of reducing feature size in the planar dimension, the patent increases density by utilizing the vertical dimension and shared structures. The shared drain electrode extends across multiple memory cells, allowing density improvement through structural sharing rather than through miniaturization of individual features. This approach avoids the need for tighter feature size control while still achieving higher density.
Data Source
AI summary
Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.