Shift Register Unit With Shared Blanking for Scan and Sense Signals
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Solution Overview
Problem
Existing gate driving circuits face challenges in efficiently outputting scan and sense driving signals with different periods and pulse widths while maintaining a simple structure, which is crucial for achieving high PPI in display devices.
Innovation Solution
A shift register unit with an input circuit, first and second control circuits, and shared blanking control circuits to manage the levels of multiple nodes, allowing simultaneous output of scan and sense driving signals for adjacent rows, reducing the number of transistors and capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate control circuits are used for scan and sense driving signals, then the signals can be output with different periods and pulse widths, but the circuit complexity and number of transistors increase
Solution Approach 1:
The patent combines the control functions for scan and sense driving signals into a single shared blanking control circuit. This circuit uses one set of control nodes (first and second control nodes) to manage both signal types, eliminating the need for separate control circuits. The shared circuit generates control signals for both scan and sense outputs using common transistors and capacitors, thereby reducing overall circuit complexity while maintaining the ability to produce signals with different periods and pulse widths through selective activation and timing control.
Solution Approach 2:
The blanking control circuit is designed with multi-functionality to handle both scan and sense driving signals. The control nodes and associated transistors serve dual purposes: they control the scan output during scan periods and the sense output during sense periods. This universal control mechanism allows a single circuit structure to perform multiple functions that would traditionally require separate dedicated circuits, thus reducing the total component count while preserving signal differentiation capabilities.
2Ease of manufacture
If the circuit structure is simplified to reduce transistor count, then manufacturing cost decreases, but the ability to manage multiple node levels for different signal periods may be compromised
Solution Approach 1:
The patent employs dynamic control mechanisms where the single blanking control circuit adaptively changes its operation mode based on timing signals. The control nodes dynamically switch between controlling scan output and sense output depending on the signal period requirements. This dynamic behavior allows the simplified circuit to maintain high adaptability in managing multiple node levels for different signal types without requiring additional static circuit elements, thereby reducing manufacturing cost while preserving functional versatility.
Solution Approach 2:
The circuit utilizes parameter changes in timing and control signal characteristics to differentiate between scan and sense driving signals. By varying the timing parameters and control signal levels dynamically, the simplified circuit structure achieves the ability to manage multiple node levels for different signal periods. This parameter-based control approach eliminates the need for complex structural modifications, reducing transistor count and manufacturing cost while maintaining the required adaptability for different signal types.
Data Source
AI summary
A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit. The input circuit is configured to control a level of a first node; the first control circuit is configured to control a level of the second node; the blanking control circuit is configured to control the level of the first node and the level of the second node; the first output circuit is configured to output a first output signal at the first output terminal; and the second output circuit is configured to output a second output signal at the second output terminal under control of the level of the second node.


