Shared Block Decoder for Nonvolatile Memory Wiring Reduction
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Solution Overview
Problem
The increasing miniaturization and higher storage densities in semiconductor memory devices lead to issues such as larger peripheral circuits and wiring congestion due to the need for more memory cells in smaller volumes, which complicates the control of memory blocks and increases the complexity of selection signals.
Innovation Solution
A nonvolatile semiconductor memory device design that reduces the number of selection signals required for selecting memory blocks by sharing multiple blocks with a single block decoder, utilizing a memory cell array with row and block decoders, and a switch circuit to connect signal lines efficiently, thereby reducing the total number of wirings and decoder components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are laminated in stacked layers to increase storage density, then storage capacity increases, but peripheral circuit area and wiring congestion increase
Solution Approach 1:
Multiple memory blocks (e.g., blocks 0-7) are merged into a single decode group that shares one block decoder. The block decoder outputs are combined through wiring sharing, where multiple block select signals (BLS<0:3>) are multiplexed onto fewer physical wiring lines (BL0-BL7), reducing the total wiring count and peripheral circuit area while maintaining the ability to address all memory blocks
Solution Approach 2:
A single block decoder is designed to serve multiple memory blocks simultaneously. The decoder performs multiple functions by decoding different block addresses and routing signals to different blocks within the decode group. The shared wiring infrastructure supports universal access to all blocks in the group, making the peripheral circuit design more efficient and scalable
2Quantity of substance
If more memory blocks are added to increase storage density, then storage capacity increases, but the number of selection signals and wiring complexity increase
Solution Approach 1:
The memory array is segmented into multiple decode groups, where each group contains a specific number of memory blocks (e.g., 8 blocks per group). Each decode group has its own shared block decoder and wiring infrastructure. This segmentation allows the system to scale to more memory blocks by adding more decode groups rather than increasing the complexity of a single large decoder, thereby managing wiring complexity through modular organization
Solution Approach 2:
The block decoder acts as an intermediary between the address input and the memory blocks. Instead of directly connecting each memory block to individual selection signals, the block decoder mediates the address decoding process and outputs block select signals that are further multiplexed through shared wiring. This intermediary structure reduces wiring complexity by consolidating multiple control signals into a smaller set of shared lines
Data Source
AI summary
A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.