Shared Boost Capacitor for SRAM Assist Circuits
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Solution Overview
Problem
In SRAMs, the decreasing chip area due to minimum feature size reduction makes it difficult to allocate adequate space for individual boost capacitors in assist circuits, limiting the ability to provide voltage boosts for high-performance read and write operations while reducing power dissipation and heat.
Innovation Solution
A common boost capacitor is used to selectively and concurrently provide voltage boosts to multiple assist circuits, including access lines and power rails, reducing the need for separate capacitors and optimizing chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual boost capacitors are allocated to each assist circuit, then voltage boost performance is improved, but chip area consumption increases
Solution Approach 1:
The patent merges multiple individual boost capacitors into a single shared boost capacitor that serves multiple assist circuits. The capacitor is shared through time-multiplexed charging and discharging, where different assist circuits access the capacitor at different times controlled by select signals. This combining approach maintains the voltage boost functionality while significantly reducing the total chip area required compared to having separate capacitors for each assist circuit.
Solution Approach 2:
The shared boost capacitor is designed to perform multiple functions by serving different assist circuits (such as read assist circuits and write assist circuits) through controlled selection. The capacitor can be charged from different sources and discharged to different circuits based on operational mode, making it a universal component that replaces multiple specialized capacitors while maintaining the necessary voltage boost performance for various memory operations.
2Area of stationary object
If minimum feature sizes are reduced, then chip area is reduced, but the ability to allocate adequate space for boost capacitors is limited
Solution Approach 1:
The patent combines multiple capacitor functions into a single shared capacitor structure, which dramatically reduces the total area required for capacitor implementation. By using one capacitor to serve multiple assist circuits through time-multiplexed access, the design accommodates capacitor requirements even in scaled technologies where individual capacitor allocation becomes impractical due to minimum feature size constraints.
3Adaptability or versatility
If multiple separate boost capacitors are implemented, then voltage boost to different circuits is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple capacitor instances into a single shared capacitor with associated control logic. Instead of having physically separate capacitors for different assist circuits, the design uses one capacitor with multiplexed charging paths and discharging paths controlled by select signals. This approach maintains the versatility of providing voltage boosts to different circuits while reducing device complexity by eliminating redundant capacitor structures and interconnections.
Solution Approach 2:
The patent introduces control logic and select signals as intermediary elements that manage access to the shared boost capacitor. These intermediaries coordinate the charging and discharging operations, ensuring that different assist circuits can access the capacitor at appropriate times without conflict. The intermediary control mechanism enables a single capacitor to effectively serve multiple functions that would otherwise require multiple separate capacitors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances writability and read stability, improves performance by applying voltage boosts to wordlines and cell supply rails, and reduces chip area requirements, increasing integrated circuit yield and reducing the probability of short circuits.
Implementation Method 1
a boost capacitor is utilized within an assist circuit to boost a line voltage above upper supply voltage VDD or below lower supply voltage VSS
Data Source
AI summary
An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) cell array and a first assist circuit and a differently configured second assist circuit. The first assist circuit is configured to apply a voltage boost to an access line utilized to access the SRAM cell array, and the second assist circuit is configured to apply a voltage boost to a voltage supply rail of the SRAM cell array. A common boost capacitor is coupled to selectively and concurrently provide a voltage boost to both the access line and the power rail via the first and second assist circuits, respectively.