Shared Branch Prediction for Stable Trace Cache Fetch

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Solution Overview

Problem

Trace caches in traditional processor designs face inefficiencies due to unexpected branch exits and high resource and power consumption, which have impeded their practical implementation.

Innovation Solution

Implementing a trace cache that caches only traces with internal control transfer instructions that meet certain stability criteria, such as being 'stable' branches, reduces the size of the trace cache needed and improves performance by ensuring the entire trace is executed when there is a hit, while sharing branch predictor resources for both instruction and trace caches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a trace cache is implemented to increase instruction fetch bandwidth and reduce power consumption, then performance and energy efficiency are improved, but the processor area and power consumption increase substantially

Engineering Contradiction:

Improveinstruction fetch bandwidthVSAvoidprocessor area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent merges the branch predictor resource between the instruction cache and trace cache by sharing the same GHP (global history pointer) and TAGE (tagged geometric length) predictor tables. This allows a single branch predictor to serve both cache systems, reducing the overall resource consumption while maintaining the performance benefits of trace caching.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The branch predictor is designed with multi-functionality to handle both instruction cache predictions and trace cache predictions. The predictor can identify and handle different types of branches (stable vs. unstable) and provide appropriate predictions for both cache systems, making the resource universally applicable and reducing the need for separate dedicated predictors.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If a trace cache is implemented to increase instruction fetch bandwidth, then performance is improved, but unexpected branch exits occur and control circuitry complexity increases

Engineering Contradiction:

Improveinstruction fetch bandwidthVSAvoidunexpected branch exits

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies different quality treatments to different branches based on their stability characteristics. Stable branches (with high prediction accuracy) are handled differently from unstable branches. The system uses stability information to determine how to handle each branch type, allowing optimized processing that reduces unexpected exits while maintaining cache effectiveness.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The system dynamically adjusts its behavior based on branch stability characteristics. The branch predictor and control circuitry adapt their handling strategies based on whether a branch is stable or unstable, allowing the system to optimize performance for predictable branches while gracefully handling unpredictable ones without causing unexpected trace exits.

Inventive Principle:

Principle #15Dynamics

3Use of energy by stationary object

If a trace cache is implemented to reduce fetch power consumption, then energy efficiency is improved, but the control circuitry requires substantial processor area

Engineering Contradiction:

Improvefetch power consumptionVSAvoidcontrol circuitry

Core Design Contradiction:

Use of energy by stationary objectVSDevice complexity

Solution Approach 1:

The patent combines the control circuitry for branch prediction into a shared resource that serves both instruction cache and trace cache. By merging the GHP and TAGE predictor tables and using a single branch predictor unit, the system reduces the control circuitry area while maintaining the power consumption benefits of trace caching.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared branch predictor serves itself by handling prediction tasks for both cache systems using the same underlying resources. The predictor uses its own stable/unstable branch identification capabilities to serve both instruction fetch and trace cache needs, reducing the overall circuitry required without sacrificing energy efficiency.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS20250362918A1Sharing Branch Predictor Resource for Instruction Cache and Trace Cache Predictions

Publication Date: 2025.11.27 APPLE INC

AI summary

Disclosed techniques relate to branch prediction and trace caching. A processor may include trace cache circuitry configured to identify and store instruction traces that include multiple predicted-taken control transfer instructions. Prediction circuitry may include table circuitry configured to store a prediction table, CTI predictor lane circuitry having multiple lanes configured to access the prediction table to predict directions of multiple control transfer instructions in a given fetch group, and trace predictor lane circuitry configured to access the prediction table to predict a direction of a final control transfer instruction in a trace cached by the trace cache circuitry. The prediction circuitry may, for a first control transfer instruction that is included in a trace as a non-terminating control transfer instruction, share a table entry in the prediction table and CTI predictor lane circuitry for both trace and non-trace predictions for the first control transfer instruction.