Shared Buffer Data Transfer for Mixed Bit-Width FIFO Paths
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Solution Overview
Problem
In data transfer devices, the difference in data processing speeds among processors leads to waiting states, and existing FIFO buffers are inefficient in managing data with varying bit widths and latencies, resulting in increased latch size and area occupancy.
Innovation Solution
A data transfer device with a shifter block generating signals of different data formats and an input/output control block that selects and controls data input/output operations, sharing a buffer block to manage data with different bit widths and latencies, allowing for reduced latch size and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a FIFO buffer is used to manage data transmission between processors with different processing speeds, then waiting states are reduced and data transfer efficiency is improved, but the latch size and area occupancy increase due to the need to accommodate data with varying bit widths and latencies
Solution Approach 1:
The patent implements dynamic configuration of the FIFO buffer by using mode signals to selectively enable different data paths and bit width configurations. The buffer can dynamically adapt its structure to match the specific data transfer requirements, enabling efficient handling of both narrow and wide data formats without requiring a fixed large buffer structure for all cases.
Solution Approach 2:
The patent changes the operational parameters of the FIFO buffer based on mode signals that indicate the current data format requirements. By adjusting parameters such as bit width, latency settings, and buffer depth according to the active mode, the system optimizes the buffer size for each specific data transfer scenario, reducing overall latch size while maintaining transfer efficiency.
2Reliability
If the buffer accommodates data with different bit widths using separate latches for each format, then data integrity is maintained, but the device complexity and area occupancy increase
Solution Approach 1:
The patent designs a universal buffer structure that can handle multiple data formats through selective configuration rather than dedicated latches for each format. The same physical buffer resources are reused across different data width modes by dynamically reconfiguring the buffer's operational parameters, thereby maintaining data integrity for various formats while reducing overall device complexity.
Solution Approach 2:
The patent merges multiple data path configurations into a single unified buffer structure. By combining the functionality of what would otherwise require separate buffers for different bit widths into one reconfigurable buffer, the system maintains the ability to preserve data integrity for each format while significantly reducing the total number of latches and overall structural complexity.
3Manufacturing precision
If dedicated buffers are allocated for each data format, then data transfer accuracy is improved, but the area occupancy and resource utilization increase
Solution Approach 1:
The patent employs dynamic reconfiguration of the buffer based on mode signals that indicate the current data format requirements. The buffer structure adaptively changes its parameters such as bit width and depth to match the active data format, ensuring accurate data transfer for each specific format while utilizing the same physical resources, thereby reducing total area occupancy compared to static dedicated buffers.
Data Source
AI summary
A data transfer device includes a shifter block that generates first and second input signals and first and second output signals, an input/output control block that selects the first input signal and the first output signal in correspondence to a mode signal and outputs an input control signal and an output control signal for controlling a data input/output operation, or selects the second input signal and the second output signal and outputs the input control signal and the output control signal, and a buffer block that latches first input data or second input data which have different data bit widths according to the input control signal, and outputs first output data or second output data which have different data bit widths according to the output control signal.