Shared Output Buffer Impedance Calibration for Compact LSI
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Solution Overview
Problem
As LSI circuits become more multifunctional, providing multiple output buffer circuits with impedance adjustment functions increases chip layout size, power consumption, and the number of pins, which complicates timing design and noise reduction.
Innovation Solution
A semiconductor device with a voltage generation circuit, comparison circuit, counter, and dummy buffer circuit that adjusts output impedance for multiple output buffer circuits, sharing these components to reduce the number of pins, power consumption, and layout size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple output buffer circuits with impedance adjustment functions are provided, then impedance adjustment capability is improved, but chip layout size increases
Solution Approach 1:
The patent merges multiple impedance adjustment circuits into a single shared circuit. The dummy buffer circuit, comparison circuit, and control logic are common to all output buffer circuits, while only the output buffers themselves are multiplied. This sharing of adjustment infrastructure dramatically reduces the area required per buffer compared to having dedicated adjustment circuits for each buffer.
Solution Approach 2:
The dummy buffer circuit serves multiple functions: it generates the reference impedance signal for the comparison circuit, provides the basis for impedance matching across all output buffers, and enables calibration for the entire system. This multi-functional design eliminates the need for separate adjustment circuits for each output buffer.
2Adaptability or versatility
If multiple output buffer circuits with impedance adjustment functions are provided, then impedance adjustment capability is improved, but power consumption increases
Solution Approach 1:
The patent combines multiple impedance adjustment operations into a single shared calibration process. The dummy buffer and comparison circuit are activated once to establish reference impedance values, which are then used by all output buffer circuits. This eliminates the need for each buffer to independently perform power-consuming calibration operations.
Solution Approach 2:
The impedance calibration is performed periodically or on-demand rather than continuously for each buffer. The shared control circuit activates the dummy buffer and comparison circuit only when calibration is needed, reducing overall power consumption compared to continuous operation of multiple independent adjustment circuits.
3Adaptability or versatility
If multiple output buffer circuits with impedance adjustment functions are provided, then impedance adjustment capability is improved, but the number of pins increases
Solution Approach 1:
The patent merges multiple calibration signal paths into a single shared path. The dummy buffer output, comparison circuit inputs, and control signals are common to all output buffers, requiring only one set of external pins for calibration rather than separate pins for each buffer's adjustment circuit.
4Measurement precision
If separate impedance adjustment circuits are provided for each output buffer circuit, then impedance adjustment precision is improved, but device complexity is increased
Solution Approach 1:
The patent segments the impedance adjustment function into two parts: a shared calibration/reference generation portion (dummy buffer and comparison circuit) and individual output buffer portions. This segmentation allows precise impedance control for each buffer while avoiding the complexity of fully independent adjustment circuits for each buffer.
Solution Approach 2:
The dummy buffer circuit acts as an intermediary that generates reference impedance signals used by all output buffers. Instead of each buffer having its own adjustment circuit, they all reference the same dummy buffer output, simplifying the overall architecture while maintaining adjustment precision through the comparison circuit's feedback mechanism.
Data Source
AI summary
When a plurality of output buffer circuits are provided, chip layout size, power consumption, and number of pins of an LSI circuit are reduced. A voltage generation circuit generates reference voltages corresponding respectively to the output buffer circuits. A comparison circuit compares the reference voltages with an output voltage of a dummy buffer circuit. A counter counts a clock signal until a comparison result of the comparison circuit matches. The dummy buffer circuit adjusts output impedance corresponding respectively to the output buffer circuits based on a count value of the counter. Adjustment value holders hold respective count values when a comparison result of the comparison circuit, obtained based on respective corresponding reference voltages, matches. The output buffer circuits respectively adjust output impedances based on respectively held count values.