Shared Buffer Memory System for Decoder Latency
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Solution Overview
Problem
Current SSD systems face challenges in optimizing read data path and control flow, leading to increased read latency and power consumption due to the need for efficient transfer of codewords between different decoding schemes, particularly with the implementation of high-density Multi-Level Cell (MLC) and Triple-Level Cell (TLC) technologies.
Innovation Solution
A memory system with a dynamic memory access (DMA) assembly, a shared memory buffer, and a memory manager that enables efficient assignment and reassignment of codewords among multiple decoders, including bit-flipping (BF) and min-sum (MS) decoders, using an early selection decoding (ESD) function to minimize transfer latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple decoders are used to process codewords from memory devices, then decoding capability and reliability are improved, but read latency and power consumption increase due to the need to transfer codewords between different decoding schemes
Solution Approach 1:
The patent merges multiple decoder operations into a unified shared buffer architecture where codewords are stored once and can be accessed by multiple decoders simultaneously. This eliminates the need to transfer codewords between different decoding schemes, reducing read latency while maintaining the ability to use multiple decoding methods (BF and MS decoders) for improved reliability.
Solution Approach 2:
The shared buffer serves multiple functions: it stores codewords for initial processing, holds intermediate results, and provides data to both BF and MS decoders. This multi-functional design allows the same buffer resource to support multiple decoding operations without requiring separate storage areas, thereby reducing overall latency.
2Reliability
If multiple decoders are used to process codewords from memory devices, then decoding capability and reliability are improved, but power consumption increases due to the need to transfer codewords between different decoding schemes
Solution Approach 1:
The patent merges multiple decoder operations into a unified shared buffer architecture where codewords are stored once and can be accessed by multiple decoders simultaneously. This eliminates the need to transfer codewords between different decoding schemes, reducing read latency while maintaining the ability to use multiple decoding methods (BF and MS decoders) for improved reliability.
Solution Approach 2:
The patent converts the potential harm of having multiple decoders (increased power consumption) into a benefit by implementing a shared buffer that allows decoders to operate independently without repeated data transfers. The shared buffer architecture enables the system to leverage multiple decoding capabilities while minimizing the power overhead through efficient resource sharing.
3Loss of time
If a shared memory buffer is used to store codewords for multiple decoders, then read latency and power consumption are reduced, but device complexity increases due to the need for memory management and control assignment
Solution Approach 1:
The shared buffer is designed with self-service capabilities where the buffer management logic is integrated directly into the buffer structure. This allows the buffer to autonomously manage codeword storage and retrieval operations, reducing the need for external control logic and simplifying the overall system architecture while maintaining low latency performance.
Data Source
AI summary
A memory system with a shared buffer architecture for multiple decoders reduces transfer latency and power consumption. Such memory system includes a memory device to generate codewords, and a dynamic memory access (DMA) assembly to receive the generated codewords. A first decoding stage of the system comprises a checksum module and a shared memory buffer, including a memory manager and destination ports, that stores and manages codewords received from the DMA assembly. A second decoding stage of the system comprises a bit-flipping (BF) decoder and a min-sum (MS) decoder, each in communication with the shared memory buffer through a respective one of the destination ports. In managing the codewords stored in the shared memory buffer, the memory manager controls assignment including reassignment of the codewords among the destination ports.