Shared Buffer Memory for Data Storage Devices

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Solution Overview

Problem

Current data storage devices face challenges in achieving high operating speed and large storage capacity while efficiently managing data transmission between hosts and storage media, particularly in portable electronic devices where mechanical drivers are absent.

Innovation Solution

A data storage device design that shares a buffer memory with a host, utilizing a micro control unit (MCU) to control data storage media and a non-volatile RAM as a buffer memory, allowing direct access and management of data and metadata between the host and storage media without MCU intervention, using various interface protocols for efficient data exchange.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a buffer memory is used to improve operating speed, then data transmission efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The buffer memory is designed to serve multiple functions: it acts as a buffer for data transmission between host and storage media, stores metadata required for device operation, and can be directly accessed by the host through a second interface. This multi-functionality improves data transmission efficiency while avoiding the need for separate dedicated buffer structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If multiple memory devices are used to increase storage capacity, then storage capacity is improved, but operating speed deteriorates

Engineering Contradiction:
Improvestorage capacityVSAvoidoperating speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The buffer memory serves as an intermediary between multiple memory devices and the host. It temporarily stores data from multiple memory devices and manages the data flow, allowing parallel operations with multiple memory devices while maintaining high operating speed through efficient buffer management.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the MCU controls all data access to ensure data consistency, then data reliability is improved, but data access speed deteriorates

Engineering Contradiction:
Improvedata consistencyVSAvoiddata access speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The buffer memory is divided into multiple regions with different access permissions. Some regions can be directly accessed by the host without MCU intervention for fast data transfer, while other regions require MCU control for metadata management and consistency. This segmentation allows simultaneous fast access and reliable control.

Inventive Principle:
Principle #1Segmentation

4Speed

If the host directly accesses the buffer memory without MCU intervention, then data access speed is improved, but control complexity increases

Engineering Contradiction:
Improvedata access speedVSAvoidinterface complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The buffer memory itself acts as an intermediary structure that the host can directly access through a dedicated second interface. This direct access path bypasses the MCU for buffer operations, improving data access speed while the MCU retains control through the first interface for coordination and metadata management.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9189397B2Data storage device including buffer memory
Publication Date: 2015.11.17 SK HYNIX INC
  • US9189397B2 patent drawing
  • US9189397B2 patent drawing
  • US9189397B2 patent drawing

AI summary

A data storage device includes a data storage medium; a micro control unit (MCU) connected to a host through a first interface method and configured to control the data storage medium in response to a request of the host; and a buffer memory connected to the host through a second interface method, connected to the MCU, and controlled by the MCU and the host, respectively.