Shared Buffer Region for Adjacent MOS Transistors
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Solution Overview
Problem
In semiconductor devices with adjacent N-channel and P-channel MOS transistors on a Silicon-on-Insulator substrate, the existing technology increases device area due to the need for separate buffer regions, leading to a reduction in breakdown voltage between the drain and source.
Innovation Solution
The semiconductor device shares a buffer region between the P-channel and N-channel MOS transistors, with the electric potential of this shared buffer region fixed to either the lowest or highest electric potential in the circuit, reducing the need for additional isolation trenches and minimizing the distance between isolation trenches and source regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate buffer regions are formed between adjacent N-channel and P-channel MOS transistors, then electrical interference between transistors is prevented, but device area increases
Solution Approach 1:
The patent merges the buffer regions of adjacent N-channel and P-channel MOS transistors into a single shared buffer region. The semiconductor layer in this shared region is doped with both N-type and P-type impurities, allowing it to serve as the buffer for both transistor types simultaneously, thereby reducing device area while preventing electrical interference.
Solution Approach 2:
The shared buffer region performs multiple functions: it serves as the buffer region for the N-channel MOS transistor, the buffer region for the P-channel MOS transistor, and provides electrical isolation for both transistors. This multi-functionality reduces the overall device area while maintaining reliability.
2Productivity
If device area is reduced by sharing buffer regions, then productivity is improved, but breakdown voltage between drain and source decreases
Solution Approach 1:
The patent applies local quality by creating distinct doped regions within the shared buffer region. The N-type impurity concentration and P-type impurity concentration are distributed differently in space, with higher N-type concentration near the N-channel transistor and higher P-type concentration near the P-channel transistor. This local variation in impurity concentration maintains adequate breakdown voltage for each transistor while enabling area reduction through sharing.
Data Source
AI summary
An object of the present invention is to provide a semiconductor device which enables to reduce the device area, while securing the breakdown voltage between the drain and the source of each MOS transistor for the semiconductor device including plural MOS transistors, which are arrayed adjacently each other, with different types of channel conductivity. The semiconductor device includes a semiconductor substrate, a buried oxide film and a semiconductor layer, and furthermore the semiconductor layer has an island-like semiconductor layer, in which a MOS transistor is formed, the MOS transistor has a source region, and a drain region that is positioned in the periphery of the source region, an island-like semiconductor layer, in which a MOS transistor is formed, the MOS transistor has a drain region, and a source region that is positioned in the periphery of the drain region, an isolation trench which isolates the former island-like semiconductor layer from other portions of the semiconductor layer, an isolation trench which isolates the latter island-like semiconductor layer from other portions of the semiconductor layer, and a buffer region, in which the electric potential is fixed to the lowest electric potential in a circuit, which prevents an electrical interference occurred between transistors.