Shared Buffer Addressing for Priority Queue Capacity Reduction

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Solution Overview

Problem

Existing buffering devices face large buffer capacity requirements due to the need for multiple queue buffers based on priority levels, leading to excessive storage capacity for transmission commands.

Innovation Solution

A buffering device manages information on write and read numbers for each grouping criterion, including priority, and holds data units in a common holding unit, forming addresses based on these numbers to reduce buffer capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple queue buffers are provided for each destination port according to priority levels, then priority-based frame transmission is enabled, but the buffer capacity becomes excessively large

Engineering Contradiction:
Improvepriority-based transmission capabilityVSAvoidbuffer capacity
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent merges multiple priority-based queue buffers into a single shared buffer memory. Instead of providing separate queue buffers for each priority level (8 queues per destination port), the invention uses one common buffer where transmission commands from different priorities are stored together, significantly reducing the total buffer capacity requirement while maintaining priority transmission capability through software-based priority management

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single shared buffer is designed to serve multiple priority levels simultaneously. The buffer structure and control logic are made universal to handle transmission commands for any priority level (0-7) and any destination port, replacing the need for dedicated buffers for each combination of priority and destination port

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If eight queue buffers are allocated per destination port for eight priority levels, then all priority levels can be supported, but the device complexity increases

Engineering Contradiction:
Improvesupport for eight priority levelsVSAvoidnumber of queue buffers
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines eight separate queue buffer structures into a single unified buffer memory with priority-based address management. The control unit implements logical separation of priorities through address calculation and management logic, eliminating the need for eight physically separate queue buffers per destination port and thereby reducing device complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single shared buffer is logically segmented into regions for different priority levels through address management. The control unit divides the buffer space virtually into eight priority segments, allowing each priority level to access its designated region without requiring physical separation, thus maintaining priority functionality while simplifying the physical structure

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12535967B2Buffering device and control method thereof
Publication Date: 2026.01.27 RENESAS ELECTRONICS CORP
  • US12535967B2 patent drawing
  • US12535967B2 patent drawing
  • US12535967B2 patent drawing

AI summary

By a buffering device, a first holding unit holds a write number value and a read number value for each of a plurality of grouping criteria. The grouping criteria include a priority of data units as one grouping parameter. A second holding unit holds a plurality of transmission commands. The plurality of transmission commands correspond to any of the plurality of grouping criteria. A control unit forms a “holding address” for causing the second holding unit to hold the written transmission commands in the second holding unit based on the write number value for the grouping criteria corresponding to the written transmission commands. The control unit forms an “output address” of the second holding unit, in which the read transmission commands are held, based on the information on the read number value for the grouping criteria corresponding to the read transmission commands.