Shared-Bus Access Interleaving for XIP Latency Bottlenecks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern integrated circuits face challenges with on-chip storage implementation due to small feature sizes, leading to latency and bus contention issues with XIP read requests, which stall subsequent write requests and hinder performance, especially in multi-core CPUs.
Innovation Solution
A bus controller is used to interleave data accesses by sequencing and prioritizing requests, allowing concurrent transactions over a shared bus, reducing idle cycles and improving throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If XIP read requests are implemented in modern integrated circuits, then storage accessibility is improved, but latency and bus contention issues occur
Solution Approach 1:
The patent segments the storage system into multiple independent storage devices (first storage device, second storage device, etc.) that can be accessed concurrently through a shared bus. By dividing the storage access into multiple parallel channels, the system achieves both improved accessibility and reduced latency through concurrent operations.
2Ease of operation
If XIP read requests are implemented, then storage accessibility is improved, but bus contention issues occur
Solution Approach 1:
The patent introduces a bus controller as an intermediary device that manages and coordinates access to the shared bus between multiple storage devices and the processor. This mediator arbitrates bus requests, schedules transactions, and prevents contention by ensuring orderly access, thereby maintaining storage accessibility while eliminating bus contention problems.
3Device complexity
If sequential processing of read requests is used, then simplicity is maintained, but subsequent write requests stall
Solution Approach 1:
The patent implements concurrent processing of read and write requests through multiple storage devices, ensuring continuous productive action. While one storage device handles a read request, another can simultaneously handle a write request, eliminating idle cycles and maintaining continuous useful action across the system, thereby improving throughput without significantly increasing complexity.
4Productivity
If concurrent transactions over shared bus are implemented, then throughput is improved, but scheduling complexity increases
Solution Approach 1:
The bus controller employs dynamic scheduling that adapts to real-time system conditions. It monitors the state of multiple storage devices and dynamically adjusts the timing and prioritization of transactions, allowing concurrent access when resources are available while automatically serializing access when contention is detected. This dynamic approach maximizes throughput while managing scheduling complexity through adaptive rather than static rules.
Data Source
AI summary
An example apparatus includes a read queue to store a first read request to access a first storage, sequencing circuitry coupled to the read queue, and prioritization circuitry coupled to the sequencing circuitry and coupled to the first storage and a second storage via a shared bus. The example sequencing circuitry is to sequence a portion of a second request to access the second storage to be interleaved with a wait interval of the first read request, the second request queued after the first read request. Additionally, the example prioritization circuitry is to generate a first transaction to access the first storage over the shared bus and a second transaction to access the second storage over the shared bus concurrently with the first transaction, the first transaction based on the first read request, the second transaction based on the second request.