Multi-Processor Debug Architecture Using a Shared System Bus

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Solution Overview

Problem

The increasing complexity of integrated-circuit chip designs, particularly those with multiple processor cores and power domains, complicates debug architectures due to the need for managing power domain crossings and signal level-shifting, which can lead to system failures and data losses.

Innovation Solution

A debug architecture that utilizes a shared main system bus for communicating debug instructions and data between processors and debug logic, reducing the need for multiple dedicated debug connections and simplifying power domain crossings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If dedicated debug bus connections are used for each processor, then debug access is provided to each processor, but the number of power domain crossings increases and system complexity increases

Engineering Contradiction:

Improvedebug accessVSAvoidsystem complexity

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

The main system bus is designed to serve dual purposes: carrying normal data traffic between processors and memory, and carrying debug instructions from debug logic to processors. This eliminates the need for separate dedicated debug bus connections for each processor, reducing the number of power domain crossings and interconnect complexity while maintaining full debug access capability to all processors.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Ease of operation

If dedicated debug bus connections are used for each processor, then debug access is provided to each processor, but the number of interconnects and power domain crossings increases

Engineering Contradiction:

Improvedebug accessVSAvoidnumber of interconnects

Core Design Contradiction:

Ease of operationVSQuantity of substance

Solution Approach 1:

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If separate debug connections are used for each processor, then each processor can be debugged independently, but manufacturing cost increases

Engineering Contradiction:

Improveindependent debug capabilityVSAvoidmanufacturing cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Reliability

If multiple dedicated debug connections are used, then comprehensive debug coverage is achieved, but the risk of data loss and metastability increases

Engineering Contradiction:

Improvedebug coverageVSAvoiddata loss and metastability

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12422478B2Debug architecture

Publication Date: 2025.09.23 NORDIC SEMICONDUCTOR

AI summary

An integrated-circuit chip and method of operating said chip is provided. The integrated-circuit chip includes multiple processors, a system memory and a main system bus for carrying data between each of the processors and the system memory. The chip also has debug logic, a debug port for communicating with the debug logic from outside the chip and a debug connection that connects the debug logic to the main system bus. A power management system is also included for controlling the power supplied to each of a number of power domains on the chip. The debug logic and each of the processors are in different respective power domains. The debug logic is configured to send a debug instruction to any of the processors. The debug instruction is communicated over the debug connection and over the main system bus.