Shared Bus Memory System Bypassing Sensing for Write Operations
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Solution Overview
Problem
Conventional semiconductor memory systems with shared common buses for volatile and non-volatile memories face inefficiencies in current and time consumption due to unnecessary sensing operations during write operations, as they cannot determine whether to perform read or write operations after an active command is applied.
Innovation Solution
A semiconductor memory system with a volatile memory and a non-volatile memory sharing a common bus, where a buffer memory temporarily stores data for read/write operations, and a memory controller transmits mode signals to differentiate between read and write modes, allowing the system to bypass sensing operations during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the non-volatile memory performs sensing operation for both read and write operations, then the memory system can operate with a unified control mechanism, but current and time are unnecessarily consumed during write operations
Solution Approach 1:
The patent applies dynamics by making the control mechanism adaptive rather than static. The memory controller dynamically adjusts the control signals based on whether a read or write operation is being performed. Specifically, the controller detects the operation type and conditionally applies sensing control signals only for read operations, while bypassing sensing for write operations. This dynamic adaptation resolves the contradiction by maintaining unified control architecture while eliminating unnecessary energy consumption during write operations.
Solution Approach 2:
The patent applies local quality by differentiating the control approach for different operation types within the same memory system. Instead of applying a uniform sensing operation to all operations, the system applies sensing control locally and selectively - enabling sensing for read operations while disabling it for write operations. This localized differentiation allows the system to optimize energy consumption for each operation type independently, resolving the contradiction between unified control and energy efficiency.
2Adaptability or versatility
If the non-volatile memory performs sensing operation for both read and write operations, then the memory system can operate with a unified control mechanism, but the time required for read/write operations increases
Solution Approach 1:
The patent applies dynamics by making the control mechanism adaptive rather than static. The memory controller dynamically adjusts the control signals based on whether a read or write operation is being performed. Specifically, the controller detects the operation type and conditionally applies sensing control signals only for read operations, while bypassing sensing for write operations. This dynamic adaptation resolves the contradiction by maintaining unified control architecture while eliminating unnecessary time consumption during write operations.
Solution Approach 2:
The patent applies local quality by differentiating the control approach for different operation types within the same memory system. Instead of applying a uniform sensing operation to all operations, the system applies sensing control locally and selectively - enabling sensing for read operations while disabling it for write operations. This localized differentiation allows the system to optimize operation time for each operation type independently, resolving the contradiction between unified control and time efficiency.
3Measurement precision
If the non-volatile memory requires more row addresses than volatile memory to select a word line, then the non-volatile memory can be addressed precisely, but the number of address pins and bus complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the address selection process into two distinct phases: a first active command phase for initial word line selection, and a second active command phase for subsequent access. This segmentation allows the non-volatile memory to use more row addresses for precise word line selection without requiring proportionally more address pins, as the addressing is distributed across multiple command cycles rather than requiring all addresses to be available simultaneously.
Solution Approach 2:
The patent applies preliminary action by performing the first active command to select the word line before the actual read or write operation. This preliminary address selection establishes the row context in advance, allowing the subsequent operation to proceed with fewer address pins actively engaged. The preliminary action phase prepares the memory structure for the main operation, reducing the instantaneous address pin requirements while maintaining precise word line selection capability.
Data Source
AI summary
Example embodiments relate to a semiconductor memory system which may include a volatile memory and a non-volatile memory that share a common bus, and a method for controlling the operation of the non-volatile memory. The semiconductor memory system may include a non-volatile memory and a memory controller. The non-volatile memory may include a buffer memory that temporarily stores data to be read from or to be written to a memory cell array, and an internal controller. The memory controller may transmits a mode signal to the non-volatile memory in response to a control signal, the control signal corresponds to either a read mode or a write mode to be applied to the non-volatile memory. In response to the mode signal, the internal controller may control the data to be read to be stored in the buffer memory, if the read mode is to be applied, and the internal controller may control the buffer memory to stand-by until a write command is received, if the write mode is to be applied.