Shared Bus Memory Architecture for Multi-Chip Data Transfer
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Solution Overview
Problem
Conventional memory systems face inefficiencies in data transmission and increased power consumption due to each memory being coupled to multiple chips on a one-to-one basis, requiring additional memory for data transmission and lacking a shared channel for direct memory-to-memory data transfer.
Innovation Solution
A memory system with a stacked memory device that allows multiple chips to share a single memory through a shared bus, enabling direct data transmission between chips without accessing the memory core, thereby increasing data transmission efficiency and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each memory is coupled to multiple chips on a one-to-one basis, then each chip can access its dedicated memory, but additional memory is required for data transmission between chips and power consumption increases
Solution Approach 1:
Multiple chips share a single memory device through a shared bus, merging what were previously separate one-to-one connections into a many-to-one shared resource configuration, eliminating redundant memory instances and reducing overall power consumption
Solution Approach 2:
The shared memory device serves multiple chips simultaneously, making the memory resource universal and multi-functional rather than dedicated to a single chip, thereby reducing the total number of memory devices needed in the system
2Ease of operation
If each memory is coupled to multiple chips on a one-to-one basis, then data access is straightforward, but data transmission between memories requires additional memory and increases power consumption
Solution Approach 1:
Multiple chips share a single memory device through a shared bus, merging what were previously separate one-to-one connections into a many-to-one shared resource configuration, eliminating redundant memory instances and reducing overall power consumption
Solution Approach 2:
The shared bus acts as an intermediary communication channel that enables direct data transmission between chips sharing the same memory, eliminating the need for additional memory devices to facilitate data transfer between chips
3Productivity
If a shared bus is used for multiple chips to access a single memory, then power consumption is reduced and bandwidth increases, but access coordination becomes more complex
Solution Approach 1:
The memory system dynamically allocates access rights to the shared bus based on current operational needs, with the controller adapting bus access permissions in real-time to optimize bandwidth utilization while managing access coordination complexity
Solution Approach 2:
The controller monitors bus usage and memory access patterns, using feedback mechanisms to dynamically adjust access coordination strategies, ensuring optimal bandwidth utilization while managing the complexity of shared resource access
Data Source
AI summary
A memory system memory system includes a first chip configured to perform a first operation, a second chip configured to perform a second operation, and a stacked memory device including a stacked structure of a plurality of memories. The stacked memory device being configured to be accessed by the first chip and the second chip through a shared bus.