Shared Serial Bus for Pin Electronics Modules
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Solution Overview
Problem
Conventional automated test equipment (ATE) for digital circuits and devices requires a large number of serial buses and I/O pins, leading to resource consumption and increased costs, as well as limitations in the number of pin electronics modules (PEMs) due to complexity in routing and pin availability.
Innovation Solution
A design that groups serial input devices into subsets with fewer control lines, where data, clock, and select lines are shared across layers, allowing for concurrent programming of PEMs using fewer control lines, reducing the number of I/O pins required and simplifying routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If each PEM is programmed via its own serial bus, then each PEM can be independently programmed, but the number of buses and I/O pins increases significantly
Solution Approach 1:
Multiple serial buses are merged into a single shared serial bus that serves multiple PEMs. The system combines data lines, clock lines, and select lines into one integrated bus structure that can address and program multiple PEMs sequentially, reducing the total number of buses from 48 to a manageable number while maintaining independent programming capability through selective addressing
Solution Approach 2:
The shared serial bus is designed to serve multiple functions and multiple PEMs simultaneously. A single bus structure with data lines, clock lines, and select lines can program any PEM in the group by activating the appropriate combination of lines, making the bus universal rather than dedicated to a single PEM
2Productivity
If more PEMs are added to increase throughput, then testing capacity increases, but the number of required pins and routing complexity increase
Solution Approach 1:
The system transitions from a flat one-to-one mapping of buses to PEMs into a multi-dimensional addressing scheme. By introducing select lines that can activate different groups or layers of PEMs, the system creates additional addressing dimensions, allowing exponential scaling of PEMs with linear increases in bus resources
Solution Approach 2:
The group of PEMs is segmented into subsets that can be independently addressed through the shared bus. Select lines divide the PEMs into manageable groups or layers, allowing the system to scale to larger numbers of PEMs by adding segments rather than requiring proportional increases in total bus resources
3Device complexity
If a shared serial bus is used to reduce the number of buses, then resource consumption decreases, but the routing becomes more complex
Solution Approach 1:
The shared bus structure is designed with local quality variations through the use of select lines that activate specific groups or layers of PEMs. This allows the routing to be optimized for different regions or groups of PEMs, making the manufacturing process more manageable by dividing the routing complexity into localized segments rather than requiring complex global routing
Data Source
AI summary
Serial input devices (e.g., pin electronics modules) are coupled to an interface via data lines, clock lines, and select lines. A first subset and a second subset of the devices are each arrayed in columns, rows, and layers. Each data line is coupled to a respective row in the first subset and a respective row in the second subset; each clock line is coupled to a respective column in the first subset and a respective column in the second subset; and each layer in each subset is coupled to a respective select line. The interface can program a device by concurrently activating one of the data lines, one of the clock lines, and one of the select lines.