Shared Cache Address Space for Peer-to-Peer Storage Nodes
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Solution Overview
Problem
Modern storage systems face limitations in scalability, performance, and host connectivity due to the direct association of caches and I/O ports with individual controllers, which restricts the capacity and availability of storage subsystems.
Innovation Solution
A peer-to-peer network architecture is introduced, where multiple modular controllers are coupled together, enabling a shared cache memory address space and direct memory access operations across nodes, facilitated by I/O adapters, memory mapping components, and an inter-node fabric, allowing for zero-copy data transfers and improved routing of I/O requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If caches and I/O ports are directly associated with individual controllers, then controller functionality is simplified and manageable, but scalability and host connectivity of the storage subsystem are limited
Solution Approach 1:
The storage subsystem is divided into multiple independent peer-to-peer controller nodes, each capable of autonomous operation. This segmentation allows the system to scale by adding more nodes while maintaining individual controller simplicity, resolving the contradiction between scalability and controller complexity.
Solution Approach 2:
Each controller node is designed with universal functionality to operate independently in the peer-to-peer network. The controllers can assume different roles (initiator, target, router) as needed, enabling flexible host connectivity without requiring complex centralized control architecture.
2Adaptability or versatility
If multiple modular controllers are coupled together in a peer-to-peer network, then scalability and host connectivity are enhanced, but system complexity and routing overhead increase
Solution Approach 1:
The peer-to-peer network employs dynamic role assignment and adaptive routing where controllers can change their operational mode based on real-time conditions. This dynamic behavior allows the network to scale flexibly while maintaining manageable complexity through automated protocol handling.
Solution Approach 2:
Each controller node autonomously manages its own routing decisions and network operations without requiring centralized control. This self-service capability enables scalability while keeping individual node complexity low, as each node independently handles its own communications and data transfers.
3Productivity
If a shared cache address space is implemented across multiple nodes, then data transfer efficiency is improved through zero-copy operations, but memory management complexity increases
Solution Approach 1:
The patent introduces a fabric interface and address mapping mechanism that mediates between the shared cache address space and physical memory locations across nodes. This intermediary layer enables zero-copy data transfers by translating logical addresses to physical locations without requiring complex distributed memory management at the application level.
Solution Approach 2:
The system implements a virtual copy of the cache address space across all peer controllers, allowing any node to access any cache memory as if it were locally attached. This virtual copying approach maintains simple memory management interfaces while enabling efficient zero-copy data transfers across the network.
4Productivity
If direct memory access operations are performed across nodes via memory mapping, then overhead is reduced and performance improves, but reliability and error handling complexity increase
Solution Approach 1:
The DMA operations across the peer-to-peer network incorporate feedback mechanisms where controllers monitor transfer status and report errors to the fabric interface. This feedback system enables high-performance direct memory access while maintaining reliability through automated error detection, reporting, and recovery protocols.
Data Source
AI summary
An apparatus for a node of a peer-to-peer network having a plurality of nodes comprises one or more I/O adapters; a cache component; one or more inter-node routing components; a memory mapping component for presenting to the I/O adapters a single address space mapped across a plurality of memory elements each associated with the cache component; and a direct memory access component for performing a memory operation on the memory elements via the memory mapping component on behalf of the I/O adapters.