Shared Cache Band Control for Heterogeneous CPU Memory Access
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Solution Overview
Problem
In multi-core CPU chips with a heterogeneous configuration, optimizing memory access for OS-dedicated CPU cores is challenging due to varying memory access request frequencies, which can lead to congestion and inefficiency in general-purpose CPU core calculations.
Innovation Solution
A shared cache unit with a memory access band control register that dynamically sets the ratio of memory access requests from OS and general-purpose CPU cores, using a request selection circuit to prioritize and manage memory access requests, ensuring optimal resource allocation and preventing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory access band from the OS-dedicated CPU core is designed to be wide, then preferential execution for OS memory access is achieved, but congestion occurs in memory accesses by general-purpose CPU cores
Solution Approach 1:
The patent implements dynamic control of memory access bands through a control register that can be modified at runtime. The bandwidth allocation between OS-dedicated CPU core and general-purpose CPU cores is not fixed but can be adjusted based on system state, allowing the system to optimize for OS priority when needed while preventing congestion during calculation-intensive periods.
Solution Approach 2:
The patent changes the bandwidth parameter of memory access dynamically by providing a control register that accepts different bandwidth settings. This allows the system to adjust the memory access band width for the OS-dedicated CPU core according to actual system needs, transforming a static design parameter into a dynamic controllable variable.
2Reliability
If memory access band for OS-dedicated CPU core is optimized at design stage, then OS interruption processing efficiency is improved, but adaptability to varying use states is reduced
Solution Approach 1:
The patent transforms the static memory access band configuration into a dynamic system by introducing a control register that can be modified at runtime. This allows the memory access band to adapt to different use states while maintaining optimized interruption processing efficiency when needed.
Solution Approach 2:
The patent enables feedback-based optimization by allowing software or system monitors to adjust the memory access band configuration based on observed system performance and workload characteristics, creating a closed-loop system that continuously optimizes for both interruption handling and overall efficiency.
Data Source
AI summary
An arithmetic processing apparatus has OS arithmetic processing unit executing instruction of OS, general-purpose arithmetic processing units each executing an instruction other than OS, a shared cache unit including a shared cache memory, a cache control unit and a request selection circuit which selects a memory access request from the arithmetic processing units, and a data buffer temporarily storing data of the memory access request, and a memory access control unit controlling a memory access to a main memory. The shared cache unit has a memory access band control register to which either one or both of a first set value, which includes an entry criterion for the request selection circuit to enter the memory access request from OS arithmetic processing unit, and a second set value which sets a capacity of a storage area in the data buffer for storing the data are set.