Shared Cache with Segmented RAM for Bit Width Conversion
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Solution Overview
Problem
Existing data processing methods in large-scale digital logic designs face challenges in efficiently utilizing cache resources and achieving high cache utilization due to limited Block RAM resources and large design area requirements, especially when dealing with bit width conversion and congestion in data communication systems.
Innovation Solution
A method and device utilizing a shared cache with N pieces of random access memory (RAM) logically divided into Y RAM segments, where data is written and read according to a fixed timeslot order, optimizing cache utilization by only processing valid bit fields and efficiently managing data flow between data buses and channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate bit width converting and splitting circuit is used to implement data bit width conversion, then bit width conversion function is achieved, but cache utilization is low and design area is large
Solution Approach 1:
The patent merges the bit width conversion function with the cache structure by integrating the DMUX de-multiplexer into the cache architecture. The cache is designed with configurable bit width conversion capability, allowing it to perform both caching and bit width conversion operations within a unified structure, thereby reducing the need for separate conversion circuits and minimizing design area.
Solution Approach 2:
The cache structure is designed to be multi-functional, serving as both a data buffer and a bit width conversion device. By configuring the cache with adjustable bit width conversion parameters, it can adapt to different conversion requirements without requiring dedicated conversion circuits, thus achieving versatility while reducing overall system area.
2Reliability
If FIFO with bit width of A + valid bit field indication width is used for each channel, then data caching is achieved, but cache resources are consumed excessively
Solution Approach 1:
The patent segments the cache structure into Y channels, where each channel has its own FIFO buffer. However, instead of allocating full-width buffers to each channel, the bit width of each channel's buffer is dynamically adjusted based on the actual data width requirements. This segmentation approach allows efficient resource utilization while maintaining reliable data caching for each channel.
Solution Approach 2:
The cache bit width parameter is made configurable and dynamic. The system adjusts the bit width of cache buffers based on the valid bit field indications and actual data requirements. This parameter change capability allows the cache to adapt its resource consumption to match the actual workload, reducing excessive resource usage while maintaining caching reliability.
3Ease of manufacture
If block RAM with limited bit width is used in FPGA implementation, then FPGA implementation is achieved, but multiple Block RAMs need to be spliced and design area is large
Solution Approach 1:
The patent makes the cache bit width a configurable parameter that can be adjusted to match the available Block RAM bit width in the target FPGA device. By parameterizing the cache structure, the design can be adapted to use existing Block RAM resources efficiently, avoiding the need to splice multiple Block RAMs and thereby reducing design area while maintaining FPGA implementability.
4Manufacturing precision
If separate bit width converting circuit is used for each channel, then bit width conversion precision is maintained, but device complexity increases
Solution Approach 1:
The patent merges the bit width conversion functionality into the shared cache structure, eliminating the need for separate conversion circuits for each channel. The unified cache structure performs bit width conversion centrally, maintaining precision through controlled data width adjustments while significantly reducing overall circuit complexity compared to having independent conversion circuits for each channel.
Data Source
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AI summary
Disclosed are a method and device for processing data, wherein the method includes: after receiving data input by a data bus, according to a destination indication of the data and a valid bit field indication of the data, writing the data input by the data bus into an uplink side shared cache; polling the uplink side shared cache according to a fixed timeslot order, reading out the data in the uplink side shared cache, outputting the data to respective corresponding channels. The embodiments of the present invention enable effective saving of cache resources, reduction of pressure on area and timing and improvement of cache utilization while reliably achieving data cache and bit width conversion.