Shared Cache Allocation Using Sub-NUMA and Client Bit Masks
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Solution Overview
Problem
In processor-based systems, running multiple applications or virtual machines on shared cache resources leads to inconsistent performance due to varying latency and resource consumption, resulting in degraded system performance.
Innovation Solution
A processor-based system with configurable combined private and shared caches uses sub-NUMA bit masks and client allocation bit masks to generate a cache allocation vector, dynamically allocating cache lines based on client ID and core availability, ensuring efficient and balanced use of shared cache resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple applications or virtual machines are run on shared cache resources, then system utilization is improved, but performance consistency deteriorates due to varying latency and resource consumption
Solution Approach 1:
The shared cache is segmented into multiple regions, with each region allocated to specific clients (applications or virtual machines) identified by client IDs. This segmentation is achieved through cache allocation structures that map client IDs to specific cache regions, ensuring that each client has dedicated cache space while the overall cache remains shared. This resolves the contradiction by maintaining high utilization through shared resources while ensuring performance consistency through dedicated allocations.
Solution Approach 2:
Different cache regions are assigned to different clients based on their specific needs and characteristics. The cache allocation is customized per client, creating local quality variations within the shared cache structure. This allows each application or virtual machine to have optimized cache access patterns specific to its workload, thereby maintaining performance consistency across multiple clients while utilizing the same shared cache resources.
2Quantity of substance
If data is allocated to portions of shared L3 cache physically distant from the processing core, then cache capacity is improved, but latency variability increases
Solution Approach 1:
The system performs preliminary actions by pre-allocating specific cache regions to clients before actual data access occurs. Cache allocation structures are pre-configured with client ID to region mappings, and allocation bit masks are pre-computed to identify available cache regions. This preliminary organization ensures that when data needs to be stored, the system can quickly identify and allocate appropriate cache regions, reducing latency variability even for physically distant cache portions.
Solution Approach 2:
Cache allocation structures and allocation bit masks serve as intermediaries between the processing core and the physically distributed cache portions. These intermediaries abstract the physical distance and complexity of cache allocation, providing a simplified interface for managing cache capacity while minimizing latency variability through efficient allocation algorithms and pre-computed masks.
Data Source
AI summary
Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system. The processor-based system is configured to receive a cache allocation request to allocate a line in a share cache structure, which may further include a client identification (ID). The cache allocation request and the client ID can be compared to a sub-non-uniform memory access (NUMA) (sub-NUMA) bit mask and a client allocation bit mask to generate a cache allocation vector. The sub-NUMA bit mask may have been programmed to indicate that processing cores associated with a sub-NUMA region are available, whereas processing cores associated with other sub-NUMA regions are not available, and the client allocation bit mask may have been programmed to indicate that processing cores are available. The sub-NUMA bit mask and the client allocation bit mask can be combined to create a cache allocation vector that a cache allocation request to allocate a line serviced by one of processing cores.