Shared Cache Line Coherency Using CCB Memory Queues
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Cache management in modern integrated circuits faces challenges in maintaining data coherency between shared cache lines and common memory, leading to issues such as cache misses and incoherent data states due to unmonitored changes in cache and common memory contents.
Innovation Solution
Implementing a compute coherency block (CCB) with memory queues (evict and miss queues) to manage cache line transfers, using snoop operations to monitor and synchronize data across multiple processor cores and common memory, ensuring coherency through Network-on-Chip (NoC) technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache lines are shared between multiple processor cores to improve data access efficiency, then processing speed is improved, but maintaining data coherency becomes more complex and error-prone
Solution Approach 1:
A compute coherency block (CCB) is introduced as an intermediary component between processor cores and the cache/memory system. The CCB includes memory queues that track cache line states and generate snoop requests to monitor and maintain data coherency across multiple cores, thereby automating the complex coherency management process while enabling shared cache access.
2Reliability
If cache memory size is increased to reduce cache misses, then data access reliability is improved, but the complexity of managing cache line transfers and coherency increases
Solution Approach 1:
The cache management system is segmented into distinct functional components: memory queues for tracking cache line states, snoop request generators for monitoring accesses, and transfer control logic for managing data movement. This segmentation allows the system to handle larger cache sizes and more complex coherency scenarios by dividing the management task into manageable, specialized units.
3Reliability
If snoop operations are implemented to monitor cache changes, then data coherency is improved, but processing overhead and time consumption increase
Solution Approach 1:
The memory queues in the CCB perform preliminary tracking of cache line states and anticipated access patterns before actual cache operations occur. By pre-establishing coherency protocols and tracking mechanisms, the system reduces the overhead of snoop operations during actual data access, as much of the coherency management is already in place.
4Measurement precision
If multiple memory queues are used to control cache line transfers, then cache management precision is improved, but device complexity increases
Solution Approach 1:
The memory queues in the CCB are designed to perform multiple functions: tracking cache line states, generating snoop requests, managing transfer priorities, and coordinating coherency protocols. This multi-functionality allows precise control of cache line transfers without proportionally increasing structural complexity, as a single queue system handles diverse management tasks.
Data Source
AI summary
Techniques for cache management based on cache management using memory queues are disclosed. A plurality of processor cores is accessed. The plurality of processor cores comprises a coherency domain. Two or more processor cores within the plurality of processor cores generate read operations for a common memory structure coupled to the plurality of processor cores. Coherency for the coherency domain is managed using a compute coherency block (CCB). The CCB includes a memory queue for controlling transfer of cache lines determined by the CCB. The memory queue includes an evict queue and a miss queue. Snoop requests are generated by the CCB. The snoop requests correspond to entries in the memory queue. Cache lines are transferred between the CCB and a bus interface unit. The transferring is controlled by the memory queue. The bus interface unit controls memory accesses.