Shared Cache Memory Controller for Low-Latency Coherent Access
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Solution Overview
Problem
In multi-core coherent systems, the varying cache structures and memory access characteristics among different processor components lead to bottlenecks in memory access latency and throughput, particularly due to the serial handling of requests by the coherence interconnect, which affects CPU stall overhead and shared memory performance.
Innovation Solution
A multi-core shared memory controller (MSMC) with integrated memory management and address translation capabilities, allowing for dynamic sharing of memories and optimized cache access through virtual to physical address translation, and using a data routing unit (DRU) to manage memory operations efficiently, including cache prewarming and DMA control messaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the coherence interconnect handles memory accesses in a serial fashion to guarantee data consistency, then data coherency is maintained, but memory access latency increases and throughput decreases
Solution Approach 1:
The memory access request is segmented into two independent parts: the critical line (data line) and the non-critical line (tag line). The critical line is transmitted first to enable quick data access, while the non-critical line follows afterward. This segmentation allows the system to prioritize data delivery without compromising coherence checks, thereby reducing overall access latency while maintaining data consistency.
Solution Approach 2:
The system performs preliminary transmission of the critical line before the non-critical line. By sending the data portion first, the system prepares the data path in advance, allowing the CPU or memory controller to begin processing the critical data while the tag validation is still in progress or completes afterward. This preliminary action reduces the effective wait time for data access.
2Loss of time
If the critical line is transmitted first to reduce CPU stall overhead, then CPU stall overhead is reduced, but other CPU's stall overhead may extend and shared memory throughput may reduce
Solution Approach 1:
The system applies different transmission priorities to different parts of the memory access request. The critical line receives high priority and is transmitted first to minimize CPU stall overhead for the requesting core. The non-critical line receives lower priority and is transmitted afterward. This local quality differentiation allows each line to be handled according to its specific needs, optimizing both CPU responsiveness and overall memory system throughput.
3Adaptability or versatility
If different components have different cache structures and access characteristics, then system functionality is enhanced, but memory access latency and throughput performance deteriorate
Solution Approach 1:
The memory controller is designed with universal functionality to handle diverse memory access requests from different types of components (CPU, DSP, GPU, etc.) with varying cache structures and access characteristics. The controller can dynamically adapt its behavior based on the request type, source component, and target memory, providing a unified interface that supports heterogeneous components while maintaining optimized throughput through the critical-line-first transmission mechanism.
Data Source
AI summary
Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.