Shared Cache Circuits for DDR DRAM Bank Group Area Reduction
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Solution Overview
Problem
The existing DDR DRAM memory architecture has a larger circuit size in the central region due to the need for separate write and read circuits for each bank group, leading to inefficiencies in data processing and increased circuit complexity.
Innovation Solution
The proposed solution involves merging specific cache and control circuits between bank groups, allowing for alternate data writing and reading without conflicts, which reduces the circuit size in the central region by sharing resources and optimizing data processing paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate write and read circuits are provided for each bank group, then data processing reliability is improved, but circuit size in the central region increases
Solution Approach 1:
The patent merges the write input cache circuits of the first and second bank groups into a single shared write input cache circuit, and merges the read output cache circuits into a single shared read output cache circuit. This consolidation reduces the number of separate circuits in the central region while maintaining the ability to independently access both bank groups, thereby reducing circuit size without compromising data processing reliability.
Solution Approach 2:
The shared write input cache circuit serves both the first and second bank groups, and the shared read output cache circuit reads data from both bank groups. This multi-functional design allows a single circuit to handle operations for multiple bank groups, reducing the overall circuit count in the central region while preserving full operational capability across all bank groups.
2Productivity
If separate write and read circuits are provided for each bank group, then data processing capability is improved, but device complexity increases
Solution Approach 1:
By combining the write input cache circuits and read output cache circuits into shared resources, the patent reduces the total number of circuit components. This merger simplifies the overall device architecture while maintaining the parallel data processing capability across multiple bank groups, as the shared caches can handle operations for both bank groups simultaneously or alternately.
Solution Approach 2:
The shared cache circuits are designed to universally serve multiple bank groups through multiplexing and control logic. This universal design reduces device complexity by eliminating redundant circuits while preserving the high data processing capability through efficient resource sharing and parallel access mechanisms.
3Productivity
If data lines from multiple bank groups are merged in a central region, then read-write efficiency is improved, but circuit size increases
Solution Approach 1:
The patent merges data lines from multiple bank groups through shared cache circuits rather than maintaining separate dedicated paths. The shared write input cache and read output cache consolidate the data flow from the first and second bank groups, improving read-write efficiency through unified data handling while reducing the circuit size by eliminating redundant data path infrastructure in the central region.
Data Source
AI summary
An embodiment provides a data processing circuit and a device. The circuit includes: a first bank group 201 and a second bank group 202; a write circuit 203; and a read circuit 204. The write circuit 203 includes a write input cache circuit 2031, and is configured to: receive stored data from a write bus 206 through the write input cache circuit 2031, write the stored data into the first bank group 201 through a first read-write bus 207, and write the stored data into the second bank group 202 through a second read-write bus 208. The read circuit 204 includes a read output cache circuit 2041, and is configured to: read the stored data from the first bank group 201 through the first read-write bus 207, and read the stored data from the second bank group 202 through the second read-write bus 208.