Shared Cache Dynamic Allocation for Pipeline Throughput

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Solution Overview

Problem

In processing pipeline architectures, dedicated buffers are inefficient as they consume valuable die area and cannot dynamically adjust to varying production and consumption rates, leading to potential stalling of upstream units.

Innovation Solution

A shared cache is used that is dynamically sized and coupled to multiple pipeline processing units and external memory, allowing storage capacity allocation as needed, with a mechanism for evicting other data before intermediate data to prevent stalling and improve throughput without dedicated buffers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dedicated buffers are used between pipeline processing units, then data storage capacity is guaranteed, but die area is consumed and buffer size cannot be dynamically adjusted

Engineering Contradiction:
Improvedata storage capacityVSAvoiddie area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The shared cache is designed to serve multiple pipeline processing units simultaneously, replacing dedicated buffers for each unit. The cache can be dynamically allocated to different producers and consumers based on runtime needs, providing universal data storage service across the pipeline while consuming shared die area rather than dedicated area for each buffer.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The buffer size is made dynamic through the shared cache allocation mechanism. Instead of fixed-size dedicated buffers, the cache can dynamically adjust the amount of storage allocated to different pipeline stages based on production and consumption rates. This allows the system to adapt buffer capacity in real-time without physical reconfiguration or consuming maximum die area for all possible buffer sizes.

Inventive Principle:
Principle #15Dynamics

2Productivity

If buffer size is increased to accommodate varying production and consumption rates, then stalling of upstream units is avoided, but die area consumption increases

Engineering Contradiction:
Improvesystem throughputVSAvoiddie area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The shared cache enables dynamic buffer size adjustment based on actual pipeline demands. When production rate exceeds consumption rate, more cache space is allocated to the producer; when consumption rate exceeds production rate, cache space is reallocated or reduced. This dynamic allocation maintains high throughput by preventing stalls while optimizing die area usage by only allocating space when needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Multiple pipeline stage buffers are merged into a single shared cache structure. Instead of having separate dedicated buffers for each pipeline stage that all consume die area simultaneously, the shared cache consolidates these storage needs into one structure that serves multiple stages, reducing total die area consumption while maintaining the ability to buffer data for throughput optimization.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If dedicated buffers are used for each pipeline processing unit, then data storage is guaranteed, but device complexity increases

Engineering Contradiction:
Improvedata storageVSAvoidbuffer management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The shared cache provides a universal storage resource that replaces multiple dedicated buffers. Instead of managing separate buffer allocations, sizes, and boundaries for each pipeline unit, the system uses a single shared cache with dynamic allocation. This reduces device complexity by eliminating the need for multiple buffer management mechanisms while guaranteeing data storage through the shared resource.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8874844B1Padding buffer requests to avoid reads of invalid data
Publication Date: 2014.10.28 NVIDIA CORP
  • US8874844B1 patent drawing
  • US8874844B1 patent drawing
  • US8874844B1 patent drawing

AI summary

A system and method for buffering intermediate data in a processing pipeline architecture stores the intermediate data in a shared cache that is coupled between one or more pipeline processing units and an external memory. The shared cache provides storage that is used by multiple pipeline processing units. The storage capacity of the shared cache is dynamically allocated to the different pipeline processing units as needed, to avoid stalling the upstream units, thereby improving overall system throughput.