Shared Cache Coherency via Instruction Data Type Tagging
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Solution Overview
Problem
In processors with shared caches, ensuring cache coherency across multiple cores is challenging, leading to potential erroneous operations when one core modifies data, and other cores access the same location expecting the original data, necessitating effective coherency protocols but still impacting performance.
Innovation Solution
Implementing a cache memory system that includes multiple cache lines with tags to store information, allowing it to determine if instructions or data are cached, invalidate cache lines as needed, and send eviction notices to higher-level memory, thereby managing cache coherency and optimizing memory access by calculating target addresses for relative-offset instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a shared cache is used to improve execution performance, then memory access speed is improved, but cache coherency errors occur when multiple cores access the same memory location
Solution Approach 1:
The cache controller performs preliminary actions by detecting instruction cache lines before data access occurs, and proactively invalidating them to prevent coherency errors. This advance detection and invalidation ensures that when data access happens, the correct data is retrieved without conflicts from stale instruction copies.
Solution Approach 2:
The patent introduces an intermediary mechanism (the cache controller with detection logic) that mediates between instruction caching and data access operations. This intermediary detects when instruction cache lines might conflict with data access and coordinates invalidation actions, acting as a mediator to maintain coherency while preserving the performance benefits of shared caching.
2Reliability
If coherency protocols are implemented to ensure data consistency, then cache coherency is improved, but processor performance deteriorates due to additional overhead
Solution Approach 1:
The system implements self-service by having the cache controller automatically detect instruction cache lines and invalidate them without requiring external intervention or complex protocol handshakes. The cache controller monitors its own state and autonomously performs invalidation operations, reducing the overhead associated with traditional coherency protocols that require inter-core communication and protocol processing.
3Productivity
If instructions are cached in the same cache as data, then cache hit rate is improved, but cache coherency conflicts increase when data is modified
Solution Approach 1:
The cache controller performs preliminary detection of instruction cache lines before data modification occurs. By identifying and invalidating instruction cache lines in advance, the system maintains the benefit of instruction caching while preventing conflicts that would arise when data is subsequently modified and needs to be accessed.
Solution Approach 2:
The patent applies local quality by treating instruction cache lines differently from data cache lines. The cache controller specifically identifies and manages instruction cache lines with special invalidation logic, while data cache lines follow standard caching behavior. This differentiated approach allows both instructions and data to be cached effectively while managing coherency conflicts through targeted invalidation of instruction copies.
Data Source
AI summary
A processor may include a cache configured to store instructions and memory data for the processor. The cache may store instructions in which a relative address, such as for a branch instruction has been calculated, such that the instruction stored in the cache is modified from how the instruction is stored in main memory. The cache may include additional information in the tag to identify an instruction entry versus a memory data entry. When receiving a cache request, the cache may look at a type tag in addition to an address tag to determine if the request is a hit or a miss based upon the request being for an instruction from an instruction fetch unit or for memory data from a memory management unit. A cache entry may be invalidated and evicted if the address matches but the data type does not match.