Shared Cache Interface Apparatus for Data Processing
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Solution Overview
Problem
Existing data processing systems face inefficiencies in transferring data between processing units due to differences in specifications and constraints, requiring temporary storage which adds circuit complexity and load, hindering immediate data transfer.
Innovation Solution
A shared cache interface apparatus that acquires data from one processing unit and outputs it to another, with a cache control mechanism that determines whether to write back data to a memory based on information from the receiving unit, reducing the need for large cache memory and optimizing data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred between processing units via a shared cache memory device, then data transfer speed is improved, but cache memory capacity requirements increase
Solution Approach 1:
The patent changes the operational parameters of the cache memory by implementing selective write-back control. The controller determines whether to write back data to main memory based on whether the data has been transferred to the destination processing unit, thereby optimizing cache utilization and reducing capacity requirements while maintaining high transfer speeds
Solution Approach 2:
The cache memory system performs self-management through automatic write-back control. The controller monitors data transfer status and autonomously decides when to write back data to main memory, eliminating the need for external intervention and reducing the burden on processing units while maintaining efficient data transfer
2Productivity
If data is cached in a shared memory device, then data transfer efficiency is improved, but power consumption increases
Solution Approach 1:
The patent optimizes power consumption by changing the operational parameters of the cache memory system. By controlling write-back operations based on actual data transfer completion, the system reduces unnecessary memory access and power consumption while maintaining high data transfer efficiency
Solution Approach 2:
The controller implements feedback control by monitoring data transfer status from processing units and using this information to determine when to write back cached data to main memory. This feedback mechanism ensures that power is consumed only when necessary for actual data transfer operations, improving overall energy efficiency
3Speed
If a shared cache memory device monitors and transfers data between processors, then data transfer speed is improved, but device complexity increases
Solution Approach 1:
The shared cache memory device is designed to perform multiple functions: caching data, monitoring write operations from multiple processing units, determining transfer necessity, and controlling write-back operations. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby managing complexity while maintaining high transfer speeds
Data Source
AI summary
There is provided with an interface apparatus. The interface apparatus provides a shared cache for a plurality of processing units. A first port acquires data from a first processing unit included in the plurality of processing units. A second port outputs the data acquired from the first processing unit to a second processing unit included in the plurality of processing units. A cache caches the data acquired from the first processing unit. A controller controls, based on information acquired from the second processing unit, whether to write back data written in the cache to a memory different from the cache.