Shared Cache Line Mode Switching for Storage Efficiency

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Solution Overview

Problem

Data processing systems face inefficiencies in cache storage capacity utilization due to the binary nature of cache mode operations (inclusive and non-inclusive modes), which either consume more storage for efficient data sharing or reduce sharing efficiency for storage savings.

Innovation Solution

A shared cache memory system that selectively operates on a cache line or range basis, switching between inclusive and non-inclusive modes based on transaction types, using state data to manage cache line storage and snoop requests, thereby optimizing storage capacity and sharing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the shared cache memory operates in inclusive mode to store cache lines in multiple caches, then data sharing efficiency is improved, but cache storage capacity is consumed

Engineering Contradiction:
Improvedata sharing efficiencyVSAvoidcache storage capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent applies dynamics by making the cache mode configurable and switchable between inclusive and non-inclusive modes. The system can dynamically adjust its operation mode based on workload characteristics, allowing it to adapt the balance between data sharing efficiency and storage capacity utilization in real-time

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameter of the shared cache memory by allowing configuration of inclusive vs non-inclusive mode. This parameter change enables the system to alter its behavior between prioritizing data sharing (inclusive mode) and prioritizing storage efficiency (non-inclusive mode)

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If the shared cache memory operates in non-inclusive mode to reduce storage usage, then cache storage capacity is saved, but data sharing efficiency deteriorates

Engineering Contradiction:
Improvecache storage capacityVSAvoiddata sharing efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The system dynamically switches between operational modes based on actual usage patterns, allowing it to adopt non-inclusive mode when storage efficiency is prioritized and inclusive mode when data sharing is more important, thus adapting to different workload scenarios

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent enables parameter change in the cache operational mode, allowing the system to adjust the inclusivity parameter based on configuration or detected workload characteristics, thereby optimizing the trade-off between storage capacity and data sharing efficiency

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If dedicated directory circuitry is used to control cache mode, then cache line mode control is achieved, but device complexity increases

Engineering Contradiction:
Improvecache line mode controlVSAvoidcontrol circuitry
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent implements self-service by having the cache memory itself store and process the mode control information. The cache memory uses its own storage resources to hold mode data and processes control decisions internally, eliminating the need for separate dedicated control circuitry and reducing overall system complexity

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9477600B2Apparatus and method for shared cache control including cache lines selectively operable in inclusive or non-inclusive mode
Publication Date: 2016.10.25 ARM LTD
  • US9477600B2 patent drawing
  • US9477600B2 patent drawing
  • US9477600B2 patent drawing

AI summary

A data processing system 2 includes a cache hierarchy having a plurality of local cache memories and a shared cache memory 18. State data 30, 32 stored within the shared cache memory 18 on a per cache line basis is used to control whether or not that cache line of data is stored and managed in accordance with non-inclusive operation or inclusive operation of the cache memory system. Snoop transactions are filtered on the basis of data indicating whether or not a cache line of data is unique or non-unique. A switch from non-inclusive operation to inclusive operation may be performed in dependence upon the transaction type of a received transaction requesting a cache line of data.