Shared Cache Memory Access for Extending Low-Power Island Memory
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Solution Overview
Problem
The challenge in integrated circuits (ICs) is to extend low-power island (LPI) memory capacity without increasing the IC's area and cost, while maintaining functionality during low-power mode operations.
Innovation Solution
Implementing a subsystem shared cache memory architecture where the LPI subsystem accesses a shared memory circuit through a subsystem memory interface in a first power mode and an LPI memory interface in a second power mode, utilizing direct mapping of memory addresses to cache lines in the shared memory circuit, eliminating the need for tag RAM in the second power mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the amount of memory in an LPI subsystem is increased to improve functionality, then the capability of the LPI subsystem is enhanced, but the area and cost of the IC increase
Solution Approach 1:
The patent merges the LPI subsystem memory with the shared cache memory system, allowing the LPI subsystem to access a portion of the shared cache memory when in low-power mode. This eliminates the need for separate dedicated memory in the LPI subsystem, thereby reducing IC area while maintaining functionality. The shared cache memory serves dual purposes: supporting both the main subsystems and the LPI subsystem.
Solution Approach 2:
The shared cache memory is designed to serve multiple functions: it acts as cache memory for the main subsystems during normal operation and as extended memory for the LPI subsystem during low-power mode. This multi-functionality allows a single memory structure to support different operational modes without requiring separate dedicated memory, thus reducing overall IC area.
2Adaptability or versatility
If the amount of memory in an LPI subsystem is increased to improve functionality, then the capability of the LPI subsystem is enhanced, but the cost of the IC increases
Solution Approach 1:
By merging the LPI memory requirements with the existing shared cache memory infrastructure, the patent eliminates the need for separate memory components and interconnect structures. This consolidation reduces manufacturing complexity and material costs, thereby lowering IC cost while maintaining LPI subsystem functionality.
Solution Approach 2:
The shared cache memory structure is designed to fulfill multiple roles across different operational modes, eliminating the need for duplicate memory components. This universality reduces the total component count and manufacturing steps, leading to lower production costs.
3Adaptability or versatility
If tag RAM is used in the shared memory circuit for dynamic cache line allocation, then memory access flexibility is improved, but power consumption increases in low-power mode
Solution Approach 1:
The patent segments the memory access paths by implementing a separate LPI memory interface that bypasses the tag RAM and subsystem memory interface when the LPI subsystem is in low-power mode. This segmentation allows the critical path for LPI memory access to be simplified, eliminating unnecessary power-consuming components while maintaining access flexibility through direct mapping.
Solution Approach 2:
The system dynamically adjusts the memory access path based on the operational mode. When the LPI subsystem is active, it uses the full subsystem memory interface with tag RAM for flexible cache management. When in low-power mode, the system switches to a simplified direct-mapped access path that eliminates tag RAM usage, thereby reducing power consumption while maintaining necessary functionality.
4Use of energy by moving object
If direct mapping is used in low-power mode to eliminate tag RAM, then power consumption is reduced, but memory access flexibility is decreased
Solution Approach 1:
The patent segments memory access flexibility into two modes: full flexibility with tag RAM during normal operation and simplified direct mapping during low-power mode. This segmentation allows the system to use only the necessary level of complexity for each operational state, reducing power consumption in low-power mode while maintaining adequate functionality.
Solution Approach 2:
The memory access architecture dynamically adapts between two configurations: a flexible tag-based system during normal operation and a simplified direct-mapped system during low-power mode. This dynamic adaptation allows the system to optimize for power consumption when full flexibility is not required, while maintaining the ability to switch back to full flexibility when needed.
Data Source
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AI summary
Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.